International Business Machines Corporation

Globalfoundries Inc.

Ultratech, Inc.

Christopher David Muzzy

Wolfgang Sauter

Jeffrey P Gambino

Timothy Harrison Daubenspeck

Timothy Dooling Sullivan

Charles Leon Arvin

David L Questad

Tom C Lee

William Thomas Motsiff

Ekta Misra

Jean E Wynne

Thomas Anthony Wassick

Jeffrey Scott Zimmerman

Charles F Musante

Zhong-Xiang He

Baozhen Li

Edmund Juris Sprogis

Robert K Leidy

Fen Chen

Brian Richard Sundlof

Kimball M Watson

Marie-Claude Paquet

Richard Steven Kontra

Gerald Matusiewicz

Theodore M Levin

Clement J Fortin

Dinesh A Badami

Anthony K Stamper

Timothy Joseph Dalton

Mark David Jaffe

Kerry Bernstein

Thomas M Shaw

Thomas Weiss

David Brian Stone

Raschid Jose Bezama

Jerome Brett Lasky

Krishna R Tunga

Mark C H Lamorey

Stephen Peter Ayotte

Paul Stephen McLaughlin

Karen P McLaughlin

George John Scott

James V Crain, Jr

Mukta G Farooq

James William Adkisson

Kevin Shawn Petrarca

Norman Jay Rohrer

Stephen Edward Greco

Eric D Perfecto

Erik L Hedberg

Paul Francis Fortier

Steven Paul Ostrander

Thomas Edward Lombardi

Brian Michael Erwin

Brian W Quinlan

Michael J Hauser

Dae Young Jung

Richard A Gilmour

Dae-Young Jung

Nathalie Normand

Judith A Wright

Jeffery P Gambino

Eric Turcotte

Dae-Young c/o Ibm United Kingdom Lim Jung

Erik Leigh Hedberg

Jean Elizabeth c/o Ibm United Kingdom Lim Wynne

Jeffrey Peter Gambino

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Mixed UBM and mixed pitch on a single die

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

Lead-free solder joining of electronic structures

Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.

Lead-free column interconnect

A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver.

Non-porous copper to copper interconnect

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core.

Conductive pillar shaped for solder confinement

A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al&#x2014;Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al&#x2014;Cr) layer directly over the Al&#x2014;Cu layer.

Corrosion resistant aluminum bond pad structure

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. A conductive via terminates at a top surface of the first conductive layer.

A chemical bath system includes a reactor tank configured to store a chemical bath solution including at least one organic element, and an organics removing chamber assembly. The organics removing chamber assembly includes at least one sub-chamber that delivers the chemical bath solution from a high-pressure section of a bath circuit to a low-pressure section. The organics removing chamber assembly modifies an amount of the at least one organic element as the chemical bath solution flows therethrough. The chemical bath system further includes an analysis/dosing controller. The analysis/dosing controller outputs a control signal that controls the organics removing chamber assembly to modify the amount of the at least one organic element in the chemical bath solution based on a comparison between an actual amount of the at least one organic element in the chemical bath solution and a desired amount of the at least one organic element.

Continuous modification of organics in chemical baths

A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver. There is also a method for joining two semiconductor substrates.

The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

Photonics chip

A method of fabricating a pillar-type connection includes forming a second conductive layer on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with a hollow core of the first conductive layer.

Growing community of inventors

Burlington, VT, United States of America

Christopher David Muzzy