Intel Corporation

Christopher D Thomas

Valery M Dubin

Jack T Kavalieros

Robert S Chau

Matthew V Metz

Mark L Doczy

Suman Datta

Justin K Brask

Uday Shah

Chris E Barns

Jihperng Leu

Chin-Chang Cheng

Madhav Datta

Paul McGregor

Harsono S Simka

Vinay B Chikarmane

Harinath Reddy

Vincent R Caillouette

A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.

Methods and apparatus for electroless plating dispense

A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

CMOS device with metal and silicide gate electrodes and a method for making it

The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.

Semiconductor device using an interconnect

A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Seed layer treatment

A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point, and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material.

Method of electroless introduction of interconnect structures

An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allow the substrate to be introduced into and removed from the processing chamber and a closed position to seal the processing chamber to allow for pressurization of the processing chamber. The processing chamber has an inlet to provide pressurizing gas, an exhaust line to exhaust pressurizing gas, a pressure regulator to regulate pressure there-within, and a sprayer to spray an electroless plating solution onto the substrate. A method for electroless spray deposition includes providing the in a processing chamber, sealing the processing chamber, pressurizing the processing chamber, regulating the pressure, and spraying an electroless plating solution onto the substrate.

Apparatus and method for electroless spray deposition

A method of treating an electroless plating waste is provided. The waste is contained and an ability of a reducing agent to reduce a metal of the waste is decreased, for example by adding a stabilizing chemical or by exposing the waste to an anode to which a positive voltage is applied. Poisonous and explosive gases evolve from the waste, which are vented. Upon completion, the waste is drained.

Method of treating an electroless plating waste

An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a different conductive shunt material.

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Aloha, OR, United States of America

Christopher D Thomas