International Business Machines Corporation

Globalfoundries Inc.

Advanced Micro Devices Corporation

Globalfoundries U.S. Inc.

Christopher D Sheraw

Judson Robert Holt

Mahender Kumar

Herbert Lei Ho

Michael D Steigerwalt

Paul A Papworth

Qiqing Christine Ouyang

Yun-Yu Wang

Timothy James McArdle

Linda R Black

Matthew W Stoker

Shreesh Narasimha

Viorel C Ontalus

Gregory Gower Freeman

Paul S Chang

Bhupesh Chandra

Yinxiao Yang

Dechao Guo

Arvind Kumar

Scott D Luning

K Paul Muller

David Michael Fried

Werner A Rausch

Anthony Gene Domenicucci

George Robert Mulfinger

Woo-Hyeong Lee

Bala S Haran

Mira Park

Sangameshwar Saudari

Alyssa C Bonnoit

Keith Kwong Hon Wong

Chengwen Pei

Eugene John O'Sullivan

Richard Stephan Wise

Andrew Herbert Simon

Unoh Kwon

Rajasekhar Venigalla

Anna Wanda Topol

Henry K Utomo

Byeong Yeol Kim

Michael P Belyansky

David M Dobuzinsky

Alessandro Cesare Callegari

Katherina E Babich

Zhibin Ren

Edward P Maciejewski

Thomas Safron Kanarsky

Claude Ortolland

Gregory Costrini

Michael Vincent Aquilino

Randolph F Knarr

Munir D Naeem

Igor V Peidous

Daewon Yang

Kai Zhao

Yue Ke

Xiaomeng Chen

Qiging Ouyang

Abu Naser M Zainuddin

Wei Ma

Massud A Aminpur

Sherry A Womack

Sangameshwar Rao Saudari

Eric T Harley

A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.

Additional spacer for self-aligned contact for only high voltage FinFETs

One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.

Integrated circuit products with gate structures positioned above elevated isolation structures

The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Methods of modulating the morphology of epitaxial semiconductor material

Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

Conformal buffer layer in source and drain regions of fin-type transistors

A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Method for controlling structure height

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.

Filling narrow openings using ion beam etch

Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a &#x3c;110&#x3e; crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the &#x3c;110&#x3e; crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Method of reducing stacking faults through annealing

The present invention provides a 'collector-less' silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

Stacking fault reduction in epitaxially grown silicon

Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

Decoder for a stationary switch machine

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Wappingers Falls, NY, United States of America

Christopher D Sheraw