Motorola Corporation

Freescale Semiconductor,inc.

Christopher C Hobbs

Philip J Tobin

Olubunmi O Adetutu

Rama I Hegde

David Gilmer

Srikanth Balaji Samavedam

William James Taylor, Jr

Bikas Maiti

Kevin D Lucas

Yeong-Jyh Tom Lii

Yolanda S Musgrove

Bich-Yen Nguyen

Marius K Orlowski

Wei E Wu

Suresh Venkatesan

Chun-Li Liu

Da Zhang

Tushar Praful Merchant

Hsing-Huang Tseng

Hsing H Tseng

Leonard John Borucki

Vidya S Kaushik

C Joseph Mogab

Larry E Frisa

Prasad V Alluri

Michael Rendon

Joe Mogab

Brad Smith

Veena Misra

Earnest B Wilson

Iuval R Clejan

Lurae G Dip

Baohong Cheng

Phillip J Tobin

Jeffrey S Cope

A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

Method of forming a semiconductor device using stress memorization

A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.

Selective metal oxide removal performed in a reaction chamber in the absence of RF activation

A semiconductor device ( ) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric ( ) is formed in a region of the device for higher voltage requirements, e.g. an I/O region ( ). A thinner second gate dielectric ( ) is formed in a region of the device for lower voltage requirements, e.g. a core device region ( ). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide ( ) is deposited over both dielectrics, followed by deposition of a gate electrode material ( ). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

Method for forming a dual gate oxide device using a metal oxide and resulting device

A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Transistor with layered high-K gate dielectric and method therefor

Techniques for forming gate dielectric layers ( ) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions ( ) are formed prior to formation of structures included in the gate structure ( ) of the semiconductor device, where the gate structures ( ) are preferably formed using low temperature operations that allow the amorphous silicon regions ( ) to remain in an amorphous state. Source/drain regions ( ) are formed in the amorphous silicon regions ( ), and then the substrate is annealed to recrystallize the amorphous regions.

Method of recrystallizing an amorphous region of a semiconductor

A transistor device ( ) utilizes a high K dielectric ( ) between a gate electrode ( ) and a substrate ( ). The high K dielectric ( ) is etched under the gate electrode ( ) so that there is an area between the gate electrode ( ) and the substrate ( ) that is void of high K dielectric ( ). The source/drains extensions ( and ) are minimized to extend substantially in alignment with the edge of gate dielectric ( ) to reduce overlap with the gate dielectric ( ). This results in reduced capacitance between the gate and the source/drain extensions. The void areas ( and ) between the gate and the substrate ( ) may remain void or may be filled with a low K dielectric, or at least a dielectric that is not high K.

Transistor having a high K dielectric and short gate length and method therefor

A zirconium oxide gate dielectric is utilized to make a transistor for an integrated circuit. In forming the transistor which uses the zirconium oxide as the gate dielectric, the zirconium oxide is etched using phosphoric acid. This phosphoric acid is a wet etch performed at an elevated temperature to achieve a simultaneous etch of a silicon nitride anti-reflective coating which overlies the gate. This use of phosphoric acid is effective because the etch is stopped by silicon oxide so that the underlying silicon substrate is protected. Also, the field oxide is not etched in any appreciable amount. Thus, the field oxide thickness is unchanged as a result of the etch.

Method for making semiconductor device

A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature. In another embodiment, reducing the metal oxide gate dielectric layer may include annealing the metal oxide layer while supplying a hydrogen-containing precursor such as silane, ammonia, germane, hydrogen, and hydrazine to the metal oxide gate dielectric layer. The gate electrode may comprise a gate electrode stack that includes a titanium nitride layer over the metal oxide gate dielectric layer and a silicon-containing capping layer over the titanium nitride layer.

Selective removal of a metal oxide dielectric

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (,) over a substrate (,). The MOS metallic gate electrode layer (,) is covered with an ARC layer (,). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (,and,) are then selectively masked photoresist (,) that is selectively exposed to deep ultraviolet (DUV) radiation (,). The ARC layer (,) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer

A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO,or a combination of SiO,, SiO,and SiO,(oxide-nitride or oxynitride) stacks.

Process for forming a high-K gate dielectric

First and second dummy structures (,and,) are formed over a semiconductor device substrate (,). In one embodiment, portions of the first dummy structure (,) are removed and replaced with a first conductive material (,) to form a first gate electrode (,) and portions of second dummy structure (,) are removed and replaced with a second conductive material (,) to form a second gate electrode (,). In an alternate embodiment, the dummy structures (,and,) are formed using a first conductive material (,) that is used to form the first electrode (,). The second electrode is then formed by removing the first conductive material (,) from dummy structures (,) and replacing it with a second conductive material (,). In accordance with embodiments of the present invention, the first conductive material and the second conductive material are different conductive materials.

Method for forming a semiconductor device

In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.

CMOS semiconductor devices and method of formation

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Tantalum oxide anti-reflective coating (ARC) integrated with a metallic

A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.

Growing community of inventors

Austin, TX, United States of America

Christopher C Hobbs