Imec Vzw

Christopher Ausschnitt

Vincent Truffert

A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w. A position-related parameter S is defined that is essentially proportional to the design widths in the range. Determination of the shift &#x3b4;S of the S parameter with respect to a pre-defined process operating point, allows to assess the critical dimension of the features produced by the process step.

Metrology method for a semiconductor manufacturing process

A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets () are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion () and a periodic portion (), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w. A position-related parameter S is defined that is essentially proportional to the design widths in the range. Determination of the shift &#x3b4;S of the S parameter with respect to a pre-defined process operating point, allows to assess the critical dimension of the features produced by the process step.

Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained 'pseudo' overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

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Heverlee, Belgium

Christopher Ausschnitt