Micron Technology Incorporated

Unity Semiconductor Corporation

Micron Quantum Devices Inc.

Ambiq Micro, Inc.

Kilopass Technology, Inc.

Hefei Reliance Memory Limited

Applied Materials, Inc.

Catalyst Semiconductor, Inc.

Round Rock Research, LLC

Rambus Inc.

Tc Lab, Inc.

Ambiq Micro, Inch

Christophe J Chevallier

Darrell Rinerson

Chang Hua Siau

Vinod C Lakhani

Steven W Longcor

Wayne I Kinney

Edmond R Ward

Robert D Norman

Steve Kuo-Ren Hsia

John Espinoza Sanchez, Jr

Seow Fong Lim

Bruce Lynn Bateman

Philip Swab

Frankie F Roohparvar

Harry Luan

Valery Axelrad

Charlie Cheng

Mathew L Adsitt

Michael S Briner

Lawrence Schloss

Roy Lambertson

Adriana Ababei

Philip F S Swab

Darrell D Rinerson

Dumitru G Cioaca

Sri Rama Namala

John Sanchez

Scott McLean Hanson

Stephen James Sheafor

Roger R Lee

Allahyar Vahidimowlavi

Benjamin S Louie

Siddarth A Krishnan

Julie Casperson Brewer

Asim A Bajwa

Steve K Hsia

See Kit Leong

Al Vahidimowlavi

Yarema A Hryciw

Deepak Chandra Sekar

Gary Bela Bronner

David A Eggleston

Daniel Martin Cermak

Chan-Sui Pang

Deepak Kamalanathan

Lidia Vereen

Elizabeth Friend

Fuxi Cai

Lawerence Schloss

Emond Ward

Frankie F Roohoarvar

Darrell D Binerson

Mehmet Gunhan Ertosun

A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.

Bias temperature instability correction in memory arrays

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Two-terminal reversibly switchable memory device

Methods and architectures for refreshing memory elements in a memory array may initialize a reference array that stores each of the possible values stored in the memory element. The values in the memory array and the reference array will drift in parallel over time. To perform a refresh, the drifted values may be read from the reference array and mapped to the original values that were stored when the reference array was initialized. Next, each value may be read from the memory array and matched with a corresponding value from the reference array. The known original value stored in the reference array can then be used to refresh the corresponding memory element in the memory array.

Retention drift correction in non-volatile memory arrays

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

Memory element with a reactive metal layer

A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.

SRAM with address dependent power usage

Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.

Non-uniform state spacing in multi-state memory element for low-power operation

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

Access signal adjustment circuits and methods for memory cells in a cross-point array

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

High voltage switching circuitry for a cross-point array

Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Preservation circuit and methods to maintain values representing data in one or more layers of memory

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

SRAM with error correction in retention mode

Growing community of inventors

Palo Alto, CA, United States of America

Christophe J Chevallier