Globalfoundries Inc.

Advanced Micro Devices Corporation

Christof Streck

Volker Kahlert

Hartmut Ruelke

Alexander Hanke

Thorsten E Kammler

Kai Frohberg

Karsten Wieczorek

John A Iacoponi

Patrick Press

Joerg Radecker

Ulrich Mayer

Guido Koerner

Georg Sulzer

Ronny Pfutzner

Andreia Ioana Popa

Heinz-Juergen Voss

Integrated circuits and methods for producing the same are provided. A method of producing the integrated circuits includes forming an insulating layer overlying a substrate. The insulating layer includes a first composition that includes silicon oxide and a porogen. The porogen is removed from the first composition to form a second composition that includes a pore, where the second composition has a dielectric constant lower than that of the first composition. An insulating layer mechanical property desired range is determined, where the second composition has an insulating material mechanical property outside of the insulating layer mechanical property desired range. The second composition is altered to form a third composition, where the third composition has the insulating layer mechanical property within the insulating layer mechanical property desired range.

Integrated circuits with an insultating layer and methods for producing such integrated circuits

By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.

Technique for forming a dielectric interlayer above a structure including closely spaced lines

A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components.

Increased density of low-K dielectric materials in semiconductor devices by applying a UV treatment

When forming complex metallization systems, a sensitive material, such as a ULK material, may be deposited on a silicon-containing dielectric material, such as an etch stop material, with superior adhesion by performing a surface treatment on the basis of fluorine radicals. Due to the fluorine treatment, silicon-fluorine bonds are generated, which are then broken up upon interacting with the chemically active component during the further deposition process. Consequently, the subsequent material layer is chemically bonded to the underlying material, thereby imparting superior stability to the interface, which in turn may result in superior robustness and reliability of the metallization system upon performing reflowing processes and operating complex packaged semiconductor devices.

Increased stability of a complex material stack in a semiconductor device by providing fluorine enriched interfaces

Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.

Methods of fabricating a semiconductor IC having a hardened shallow trench isolation (STI)

During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. In one embodiment, a semiconductor device is provided that includes a metallization system formed above a substrate. The metallization system includes a metal line formed in a dielectric layer and having a top surface. The metallization system also includes a conductive cap layer formed on the top surface. A via extends through the conductive cap layer and connects to the top surface of the metal line. A conductive barrier layer is formed on sidewalls of the via. An interface layer is formed of a noble metal between the conductive cap layer and the conductive barrier layer and between the top surface of the metal line and the conductive barrier layer.

Metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices

By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride

By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.

Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer

During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.

Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ALD techniques

During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. Hence, well-established wet chemical etch chemistries may be used while not unduly contributing to process complexity.

Method of fabricating a metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices

Method of manufracturing increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride

Nickel silicide is formed on the basis of a gaseous precursor, such as nickel tetra carbonyl, wherein the equilibrium of the decomposition of this gas may be controlled to obtain a highly selective nickel silicide formation rate. Moreover, any etch step for removing excess nickel may be avoided, since only minute amounts of nickel may form on exposed surfaces, which may then be effectively removed by correspondingly shifting the equilibrium. Consequently, reduced process complexity, enhanced controllability and enhanced tool lifetime may be obtained.

Technique for forming nickel silicide by depositing nickel from a gaseous precursor

A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. The recess is filled with a material comprising silver.

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Coswig, Germany

Christof Streck