3d Plus

Thomson-csf

Compagnie D'informatique Militaire Spatiale Et Aeronautique

Other

Packaging Sip

Compagnie D'informatique Militaire Spatiale & Aeronautique

Christian Val

Olivier Lignier

Alexandre Val

Michel Leroy

Didier Pribat

Guy Le Parquier

Claude Vergnolle

Francois Lambert

Andre Gerard

Regis Bocage

Dominique Gilet

Jacques Le Ny

Joseph Pinel

Pascal Couderc

Yves Van Campenhout

Yves B Gibod

The field of the invention is that of producing 3D electronic modules, compatible with components operating beyond 1 GHz. The invention relates to a 3D electronic module featuring an interconnection between a horizontal conductor and a vertical conductor to which it is connected exhibits, in a vertical plane, a non-zero curvature. It also relates to the associated production process.

Process for producing a high-frequency-compatible electronic module

An electronic module including one or more electronic components that are electrically connected to a multilayer PCB circuit comprises, on one face, electrical connection balls for the external electrical connection of the electronic module. The PCB circuit comprises a hermetically protective electrically insulating inorganic inner layer, and the module comprises six faces with an electrically insulating or conductive inorganic hermetic protection layer on the five faces other than that formed by the PCB circuit.

Process for the wafer-scale fabrication of hermetic electronic modules

The invention relates to a 3D electronic module including, in a direction referred to as the vertical direction, a stack () of electronic dice (), each die including at least one chip () provided with interconnect pads (), this stack being attached to an interconnect circuit () for the module provided with connection bumps, the pads () of each chip being connected by electrical bonding wires () to vertical buses () that are themselves electrically linked to the interconnect circuit () for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, characterized in that each electrical bonding wire () is linked to its vertical bus () by forming, in a vertical plane, an oblique angle (&#x3b1;) and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another die and the corresponding vertical bus, and this is obtained by wiring the bonding wire in a non-rectilinear manner to compensate for the difference in vertical length of the vertical bus from one die to the other, such that the electrical conductor between the pad of a chip of one die and the interconnect circuit, and the electrical conductor between said same pad of a chip of the other die and the interconnect circuit, are the same length.

Method of miniaturized chip on chip interconnection of a 3D electronic module

A 3D electronic module comprises: two electrically tested electronic packages, each comprising at least one encapsulated chip and output balls on a single face of the package, referred to as the main face; two flexible circuits that are mechanically connected to one another, each being associated with a package, and which are positioned between the two packages, each flexible circuit comprising: on one face, first electrical interconnect pads facing the output balls of the associated package; at its end, a portion that is folded over a lateral face of the associated package; second electrical interconnect pads on the opposite face of this folded portion.

3D electronic module comprising a ball grid array stack

A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages, several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers, dicing of the stacked reconstituted wafers to obtain 3D modules.

Method of collective fabrication of 3D electronic modules configured to operate at more than 1 GHz

A method for collectively fabricating a reconstituted wafer comprising chips exhibiting connection pads on a front face of the chip, comprises: positioning the chips on an initial adhesive support, front face on the support, vapor deposition at atmospheric pressure and ambient temperature, of an electrically insulating layer on the initial support and the chips, having a mechanical role of holding the chips, transfer of the chips covered with the mineral layer onto a provisional adhesive support, rear face of the chips toward this provisional adhesive support, removal of the initial adhesive support, overlaying the chips onto a support of 'chuck' type, front faces of the chips toward this support, removal of the provisional adhesive support, deposition of a resin on the support of 'chuck' type to encapsulate the chips, and then polymerization of the resin, removal of the support of &#x201c;chuck&#x201d; type, production of an RDL layer active face side.

Method for producing reconstituted wafers with support of the chips during their encapsulation

A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.

Method for positioning chips during the production of a reconstituted wafer

A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, molding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the 'stack of panel' assembly for the purpose of obtaining the 3D electronic modules.

Method for collective fabrication of 3D electronic modules comprising only validated PCBs

A process for the vertical interconnection of 3D electronic modules (), a module comprising a stack of K electronic wafer levels () electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer.

Process for the vertical interconnection of 3D electronic modules by vias

A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

A process for the wafer-scale fabrication of CMS electronic modules starts from a wafer with metallized outputs, comprising electronic components molded in resin and, on one side, the external outputs of the electronic components on which a nonoxidizable metal or alloy is deposited, and of a printed circuit provided with oxidizable metal or alloy contact pads. In the process, the wafer is cut in predetermined patterns for obtaining reconfigured molded components that include at least one electronic component; the reconfigured components are assembled on the printed circuit, the metallized external outputs of the reconfigured components being placed opposite the metallized contact pads of the printed circuit; and these external outputs are connected solderlessly to the metallized contact pads of the printed circuit by means of a material based on an electrically conductive adhesive or ink.

Process for the wafer-scale fabrication of electronic modules for surface mounting

The invention relates to a 3D electronic module comprising a stack () of at least a first slice () and a second slice (), the first slice () having on a face () at least one set () of electrically conductive protrusions (), and the second slice () comprising at least one zone () of electrically insulating material, traversing the thickness of the slice. The second slice () comprises at least one electrically conductive element () traversing said slice in a zone () of electrically insulating material, able to receive a set () of protrusions () of the first slice ().

3D electronic module

The invention relates to an electronic module comprising a stack of n packages of predetermined thickness E, which are provided on a lower surface with connection balls of predetermined thickness e, said connection balls being connected to a printed circuit for interconnecting the package. The printed circuit is placed on the lower surface of the package level with the balls, is drilled with metallized holes, in which the balls are located and to which they are connected, and has a thickness eless than eso as to obtain a module with a total thickness not exceeding n (E+10% e).

Low-thickness electronic module comprising a stack of electronic packages provided with connection balls

The invention relates to a method of interconnecting electronic components of a first wafer (T) with electronic components of a second wafer (T), each wafer having metallized vias () which pass through the wafer in the thickness direction. The method includes deposition of a drop () of conductive ink containing solvents on each via () of the first wafer (T); stacking of the second wafer (T) on the first so that the vias () of the second wafer (T) are substantially superposed on the vias () of the first wafer (T); removal of 50 to 90% of the solvents contained in the drops () by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops () so as to produce electrical connections () between the superposed metallized vias ().

Method of interconnecting electronic wafers

The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer () of thickness ecomprising silicon, covered on one face with electrical connection pads (), called test pads, and then with a thin electrically insulating layer () of thickness e, forming the insulating substrate provided with at least one silicon electronic component () having connection pads () connected to the test pads () through the insulating layer. The components are encapsulated in an insulating resin () of thickness e, filling the spaces between the components, then separated from one another by first grooves () with a width Land a depth Psuch that e+e&#x3c;Pe+e+e, the connection pads of components () being connected to tracks () that are flush with the grooves (); This step, repeated K times, is followed by a step of stacking the K wafers, of forming metallized holes in the thickness of the stack, which are intended for connecting the dies together, and then of dicing the stack in order to obtain the n 3D modules.

Growing community of inventors

St. Remy les Chevreuse, France

Christian Val