Intel Corporation

Infineon Technologies Ag

Infineon Technologies Austria Ag

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Intel IP Corporation

Intel IP Corportaion

Google Inc.

Christian Geissler

Georg Seidemann

Sven Albers

Thorsten Meyer

Andreas Wolter

Klaus Reingruber

Gerald Ofner

Marc Dittes

Thomas Wagner

Richard Patten

Reinhard Mahnkopf

Andreas Augustin

Sonja Koller

Claus Waechter

Franz Hirler

Ralf Siemieniec

Bernd Waidhas

Maciej Wojnowski

Matthias Steiert

Christian Mueller

Frank Zudock

Klaus Elian

Oliver Blank

Walter Hartner

Bernhard Winkler

Maximilian Roesch

Thomas Kilger

Johannes Lodermeyer

Florian Brandl

Jan Proschwitz

Robert Gruenberger

Martin Richard Niessner

Teodora Ossiander

Franz-Xaver Muehlbauer

Karolina Zogal

Klaus Jürgen Reingruber

Horst Theuss

Jens G Pohl

Gottfried Beer

Danny Pak-Chum Shum

Markus Brunnbauer

Rainer Markus Schaller

David Tumpold

Bernd Goller

Chau Fatt Chiang

Dominic Maier

Chee Yang Ng

Franz Schuler

Ludwig Heitzer

Bernhard Rieder

Klaus Pressel

Thomas Ort

Robert Fehler

Cyrus Ghahremani

Beng Keh See

Derek Debie

Francesca Arcioni

Andreas Allmeier

David O'Sullivan

Tuncay Erdoel

Gerhard Haubner

Alexandra Atzesdorfer

A semiconductor apparatus comprises: a circuit board; a semiconductor package having a main surface, wherein the semiconductor package is arranged on the circuit board and the main surface faces the circuit board; a radio-frequency line element of the semiconductor package, which radio-frequency line element is arranged on the main surface or inside the semiconductor package, wherein the radio-frequency line element is designed to transmit a signal at a frequency of greater than 10 GHz; and an underfiller material arranged between the circuit board and the semiconductor package, wherein the radio-frequency line element and the underfiller material do not overlap in an orthogonal projection onto the main surface.

Semiconductor apparatuses with radio-frequency line elements, and associated manufacturing methods

A radiation source device includes at least one membrane layer, a radiation source structure to emit electromagnetic or infrared radiation, a substrate and a spacer structure, wherein the substrate and the at least one membrane form a chamber, wherein a pressure in the chamber is lower than or equal to a pressure outside of the chamber, and wherein the radiation source structure is arranged between the at least one membrane layer and the substrate.

Radiation source device

A radio-frequency device comprises a printed circuit board and a radio-frequency package having a radio-frequency chip and a radio-frequency radiation element, the radio-frequency package being mounted on the printed circuit board. The radio-frequency device furthermore comprises a waveguide component having a waveguide, wherein the radio-frequency radiation element is configured to radiate transmission signals into the waveguide and/or to receive reception signals via the waveguide. The radio-frequency device furthermore comprises a gap arranged between a first side of the radio-frequency package and a second side of the waveguide component, and a shielding structure, which is configured: to permit a relative movement between the radio-frequency package and the waveguide component in a first direction perpendicular to the first side of the radio-frequency package, and to shield the transmission signals and/or the reception signals in such a way that a propagation of the signals via the gap is attenuated or prevented.

Radio-frequency devices and methods for producing radio-frequency devices

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

Package stacking using chip to wafer bonding

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.

Integration of stress decoupling and particle filter on a single wafer or in combination with a waferlevel package

An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

Wafer level package structure with internal conductive layer

A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

Semiconductor devices having cutouts in an encapsulation material and associated production methods

An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

Electronic device including redistribution layer pad having a void

An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

Semiconductor die package with more than one hanging die

Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

Integrated circuit packages including an optical redistribution layer

A production method includes providing a semiconductor substrate with a wiring layer stack having cutouts on a first main surface region of the semiconductor substrate at which MEMS components are arranged in an exposed manner in the cutouts and projecting through contact elements are arranged at metallization regions of the wiring layer stack; applying a b-stage material layer cured in an intermediate stage on the wiring layer stack, such that the cutouts are covered by the b-stage material layer and the vertically projecting through contact elements are introduced into the b-stage material layer; curing the b-stage material layer to obtain a cured b-stage material layer; thinning the cured b-stage material layer; and applying a redistribution layer (RDL) structure on the thinned, cured b-stage material layer to obtain an electrical connection between the wiring layer stack and the RDL structure via the through contact elements.

Method for producing packaged MEMS assemblies at the wafer level, and packaged MEMS assembly

Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

Electronic components having three-dimensional capacitors in a metallization stack

Growing community of inventors

Teugn, Germany

Christian Geissler