International Business Machines Corporation

Elpis Technologies Inc.

Adeia Semiconductor Bonding Technologies Inc.

Choonghyun Lee

Kangguo Cheng

Takashi Ando

Jingyun Zhang

Juntao Li

Alexander Reznicek

Pouya Hashemi

Hemanth Jagannathan

Shogo Mochizuki

Peng Xu

Ruqiang Bao

Soon-Cheon Seo

Injo Ok

Seyoung Kim

Chun Wing Yeung

Heng Wu

Xin Miao

Paul Charles Jamison

Brent A Anderson

Vijay Narayanan

Christopher Joseph Waskiewicz

Ruilong Xie

Robin Hsin Kuo Chao

Chanro Park

Koji Watanabe

Richard Glen Southwick, Iii

Junli Wang

Zheng Xu

Zhenxing Bi

Reinaldo Ariel Vega

Yann Mignot

Kisik Choi

Miaomiao Wang

Adra Carr

Robin H Chao

Robinhsinku Chao

Nicolas J Loubet

Dechao Guo

Wilfried Haensch

Richard Anthony Conti

Michael P Belyansky

Gen Tsutsui

Youngseok Kim

Kisup Chung

SangHoon Shin

Richard G Southwick

Chih-Chao Yang

Bahman Hekmatshoartabari

Tak H Ning

Oleg Gluschenkov

Wenyu Xu

Fee Li Lie

Oscar Van Der Straten

Sanjay C Mehta

Koichi Motoyama

Li-Wen Hung

Joseph F Maniscalco

Hari V Mallela

Timothy Mathew Philip

Dimitri Houssameddine

Sungjae Lee

Sanghoon Shin

A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Gate stack quality for gate-all-around field-effect transistors

A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Vertical field effect transistor with low-resistance bottom source-drain contact

Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion

A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

Structure and method to fabricate resistive memory with vertical pre-determined filament

A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.

Tri-layer STI liner for nanosheet leakage control

A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Semiconductor device and method of forming the semiconductor device

Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.

Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.

Vertical transport field-effect transistors having germanium channel surfaces

A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.

Formation of wrap-around-contact for gate-all-around nanosheet FET

A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

Multi-threshold voltage gate-all-around transistors

Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Replacement-channel fabrication of III-V nanosheet devices

Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

Dual damascene crossbar array for disabling a defective resistive switching device in the array

A semiconductor device and method of forming a semiconductor device are provided. The semiconductor device includes a pore-type heater having a center pore recess. The semiconductor device further includes a tapered structure formed on the pore-type heater and having a tip portion at least extending down to the center pore recess. The semiconductor device also includes a containment layer confining volatile active material during any of a fabrication and an operation of the semiconductor device performed above a threshold temperature.

Phase change memory structure with efficient heating system

Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

Resistive random-access memory

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Rensselaer, NY, United States of America

Choonghyun Lee