Samsung Electronics Co., Ltd.

Choongbin Yim

Jongbo Shim

Jihwang Kim

Jin-Woo Park

Jungwoo Kim

Kyoungsei Choi

Taesung Park

Young Lyong Kim

Jinwoo Park

Mi-Yeon Kim

Hae-Jung Yu

Younji Min

Donghan Kim

Dongwook Kim

Jinho Lee

Dongho Kim

Doohwan Lee

Yongkwan Lee

Hyunki Kim

Dae-Young Choi

Jiyong Park

Hyeongmun Kang

Eunchul Ahn

Seungkon Mok

Hwan Pil Park

Sungkyu Park

Jungsoo Byun

Junggon Choi

Byoungwook Jang

PaLan Lee

Sungeun Pyo

Sungbum Kim

Provided is a semiconductor package including a support wiring structure, a semiconductor chip on the support wiring structure, a cover wiring structure on the semiconductor chip, and a filling member filling between the support wiring structure and the cover wiring structure, wherein the cover wiring structure includes a cavity which extends from a lower surface of the cover wiring structure into the cover wiring structure and in which an upper portion of the semiconductor chip is positioned, and a first slot and a second slot respectively having a first width and a second width in a first horizontal direction, the first slot and the second slot communicating with the cavity, and respectively extending to a first side surface and a second side surface of the cover wiring structure, which are opposite to each other in a second horizontal direction which is orthogonal to the first horizontal direction of the cover wiring structure.

Semiconductor package having semiconductor chip positioned in cavity of cover wiring structure

A semiconductor package includes: a package substrate; a semiconductor chip mounted above the package substrate; a chip connection terminal interposed between the semiconductor chip and the package substrate; an adhesive layer disposed on the package substrate and that covers a side and a top surface of the semiconductor chip and surrounds the chip connection terminal between the semiconductor chip and the package substrate; a molding layer disposed on the package substrate and that surrounds the adhesive layer; an interposer mounted on the adhesive layer and the molding layer, where the interposer includes an interposer substrate; and a conductive pillar disposed on the package substrate, where the conductive pillar surrounds the side of the semiconductor substrate, penetrates the molding layer in a vertical direction and connects the package substrate to the interposer substrate.

Semiconductor package and manufacturing method thereof

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

Semiconductor package

A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.

Semiconductor package structure having interposer substrate, and stacked semiconductor package structure including the same

A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

Semiconductor package including interposer and method of manufacturing the semiconductor package

A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

Semiconductor package substrate and semiconductor package including the same

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

Methods of manufacturing semiconductor packages

A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

Interposer and semiconductor package including the same

A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

Semiconductor package, and package on package having the same

Semiconductor package with interposer

Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.

Semiconductor packages and methods of manufacturing the same

A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.

Package-on-package electronic devices including sealing layers and related methods of forming the same

A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

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Cheonan-si, South Korea

Choongbin Yim