Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Lg Electronics Inc.

Stats Chippac Pte. Ltd.

Amkor Technology Korea, Inc.

Other

Choon Heung Lee

Jin Young Kim

Sang Jae Jang

Glenn A Rinne

Doo Hyun Park

Chul Woo Park

Ju Hoon Yoon

Ji Young Chung

Sung Kyu Kim

Seong Min Seo

Sung Su Park

Sun Goo Lee

Sang Ho Lee

Seon Goo Lee

Jong Sik Paek

Sang Won Kim

In Bae Park

Sang Gyu Lee

Jun Young Yang

Suk Gu Ko

Boo Yang Jung

In Hwan Choi

Jin Pil Kim

Jae Hyung Song

Chul Soo Lee

Jong Yeul Suh

Seung Jae Lee

Young Ho Kim

Byong Jin Kim

HunTeak Lee

Jin Han Kim

Se Woong Cha

Yoon Joo Kim

No Sun Park

Donald Craig Foster

Jae Dong Kim

Do Hyun Na

Wan Jong Kim

JunHo Ye

Sung Soon Park

Jeoung Kyu Choi

Kyong Hoon Youn

Ki Cheol Bae

Gi Jeong Kim

Min Ho Kim

Won Bae Bang

Akito Yoshida

Won Sun Shin

Eun Sook Sohn

Eun Joo Kim

Sung Sik Jang

Choong Hoe Kim

Yang Gyoo Jung

Chang Deok Lee

Chan Ha Hwang

Tae Hoan Jang

Dong Su Ryu

Won Dai Shin

Ho Cheol Jang

Won Kyun Lee

Jong Woon Choi

Su Yol Yoo

Teag Il Cho

Seok Hyun Choi

Jong Hae Hyun

Chang Hoon Ko

A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

Semiconductor device with redistribution layers formed utilizing dummy substrates

Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.

Semiconductor device using EMC wafer support system and fabricating method thereof

A semiconductor device has an electrical component assembly, and a plurality of discrete antenna modules disposed over the electrical component assembly. Each discrete antenna module is capable of providing RF communication for the electrical component assembly. RF communication can be enabled for a first one of the discrete antenna modules, while RF communication is disabled for a second one of the discrete antenna modules. Alternatively, RF communication is enabled for the second one of the discrete antenna modules, while RF communication is disabled for the first one of the discrete antenna modules. A bump is formed over the discrete antenna modules. An encapsulant is deposited around the discrete antenna modules. A shielding layer is formed over the electrical components assembly. A stud or core ball can be formed internal to a bump connecting the discrete antenna modules to the electrical component assembly.

Semiconductor device and method of forming discrete antenna modules

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Wafer level fan out semiconductor device and manufacturing method thereof

A semiconductor device has an electronic component assembly, and a plurality of discrete antenna modules disposed over the electronic component assembly. Each discrete antenna module is capable of providing RF communication for the electronic component assembly. RF communication can be enabled for a first one of the discrete antenna modules, while RF communication is disabled for a second one of the discrete antenna modules. Alternatively, RF communication is enabled for the second one of the discrete antenna modules, while RF communication is disabled for the first one of the discrete antenna modules. A bump is formed over the discrete antenna modules. An encapsulant is deposited around the discrete antenna modules. A shielding layer is formed over the electronic components assembly. A stud or core ball can be formed internal to a bump connecting the discrete antenna modules to the electronic component assembly.

In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

Method for fabricating semiconductor package having a multi-layer molded conductive substrate and structure

A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.

Semiconductor package and manufacturing method thereof

Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

Laser assisted bonding for semiconductor die interconnections

Growing community of inventors

Seoul, South Korea

Choon Heung Lee