Samsung Electronics Co., Ltd.

Chong-Kwang Chang

Jung-Gun You

Sung-Min Kim

Hyung-Jong Lee

Hong-Jae Shin

Young-Mook Oh

Hyo-Jeong Kim

Nae-in Lee

Gi-Gwan Park

Moon-han Park

Dong Suk Shin

Baik-Min Sung

In-Keun Lee

Dong-hoon Khang

Dong-woo Kang

Hak-yoon Ahn

Ji-ho Yoo

Seung-Il Bok

Kwang-Hyeon Baik

Sung-Hon Chi

Yong-Jin Chung

Ju-Beom Yi

Oh-Sang Cho

A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

Semiconductor device

An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.

Method of manufacturing integrated circuit device

A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.

Semiconductor devices and methods of manufacturing the same

A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Method of fabricating semiconductor integrated circuit device

A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

Method of manufacturing semiconductor device

An apparatus for etching an edge of a wafer includes a chamber, a chuck disposed inside the chamber upon which the wafer is disposed, a plate spaced apart from the wafer and disposed above the wafer, and an edge ring formed along the edge of the wafer and combined with an outer periphery of the plate, wherein the edge ring comprises a ring base spaced a distance apart from the wafer to form a parallel plane with respect to the wafer, and a first ring protrusion protruding from the ring base to insulate the edge of the wafer from a central region of the wafer.

Apparatus for etching edge of wafer

A semiconductor integrated circuit memory device includes a gate line that extends in a first direction, an active region adjacent to a first end of the gate line and that extends in a second direction, a silicide layer formed on a top surface of the active region, on a top surface of the gate line, on both sidewalls of the first end of the gate line, and on a transverse endwall of the first end of the gate line. A spacer may be formed on sidewalls of the gate line, excluding the first end of the gate line, and a contact shared by the active region may be formed on the first end of the gate line.

Semiconductor integrated circuit device

Growing community of inventors

Bucheon-si, South Korea

Chong-Kwang Chang