Intel Corporation

Tahoe Research, Ltd.

Chong J Zhao

James A McCall

George Vergis

Kuljit Singh Bains

Shigeki Tomishima

Bill Nale

Pete D Vogt

Christopher E Cox

Jeffory L Smalley

Dimitrios Ziakas

Suneeta Sah

John R Goles

Jonathan W Thibado

Rajat Agarwal

Zhichao Zhang

Sanka Ganesan

Ram S Viswanath

Xiang Li

Rajasekaran Swaminathan

Bassam N Coury

Yidnekachew S Mekonnen

Kuang C Liu

David J Llapitan

Gregorio R Murtagian

Mohanraj Prabhugoud

Mani Prakash

John M Lynch

John C Gulick

Phi Hung Thanh

Michael Gutzmann

Robert J Friar

Thomas T Holden

San K Chhay

A stack of memory chips and a logic chip is placed within a same package. Multiple memory chips of the stack of memory chips are divided into fractions, and multiple internal channels within the package that emanate from the logic chip are coupled to respective ones of the fractions. The logic chip has a multiplexer, including a multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Stacked memory chip solution with reduced package inputs/outputs (I/Os)

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Techniques to couple high bandwidth memory device on silicon substrate and package substrate

Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

Package pin pattern for device-to-device connection

Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

Interposer and electronic package

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.

Integrated memory coplanar transmission line package having ground path that brackets data path to extend memory speeds

A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

DIMM for a high bandwidth memory channel

Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Techniques to access or operate a dual in-line memory module via multiple data channels

Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

CPU package substrates with removable memory mechanical interfaces

Growing community of inventors

West Linn, OR, United States of America

Chong J Zhao