Megica Corporation

Megit Acquisition Corp.

Qualcomm Incorporated

Megit Acquistion Corp.

Chiu-Ming Chou

Mou-Shiung Lin

Chien-Kang Chou

Hsin-Jung Lo

Ying-Chih Chen

Ching-San Lin

Jin-Yuan Lee

Shih-Hsiung Lin

Chu-Fu Lin

Ke-Hung Chen

Wen-Chieh Lee

Yi-Cheng Liu

Nick Kuo

Li-Ren Lin

Huei-Mei Yen

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

Chip package and method for fabricating the same

A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.

Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer

A method for fabricating an integrated circuit (IC) chip includes providing a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, next forming a first titanium-containing layer over the pad exposed by the opening, next performing an annealing process by heating the titanium-containing layer at a temperature of between 300 and 410&#xb0; C. for a time of between 20 and 150 minutes in a nitrogen ambient with a nitrogen purity of great than 99%, next forming a second titanium-containing layer on the first titanium-containing layer, and then forming a metal layer on the second titanium-containing layer.

Integrated circuit (IC) chip and method for fabricating the same

A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.

Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures

A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

Very thick metal interconnection scheme in IC chips

A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.

Chip structure

A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Stacked chip package with redistribution lines

A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

Metal pad or metal bump over pad exposed by passivation layer

A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Semiconductor chip with coil element over passivation layer

This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer; forming a metal pad layer on the adhesive/barrier layer; bonding a wire onto the metal pad layer to form a ball bond thereon; and after forming the ball bond on the metal pad layer, running the wire so as to contact the wire with a second bonding pad and forming a wedge bond thereto.

Wire bonding method for preventing polymer cracking

The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Semiconductor chip with post-passivation scheme formed over passivation layer

A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

Semiconductor chip with a bonding pad having contact and test areas

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Top layers of metal for integrated circuits

The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Semiconductor chip with passivation layer comprising metal interconnect and contact pads

A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 &#x3bc;m.

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Kao-Hsiung, Taiwan

Chiu-Ming Chou