Industrial Technology Research Institute

Worldwide Semiconductor Manufacturing Corporation

Ching-Yuan Ho

Shang-Yun Hou

Yung-Hsiang Chen

Heng-Yuan Lee

Lurng-Shehng Lee

Chieh-Shuo Liang

Chen-Hsin Lien

A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A dielectric layer is formed on the semiconductor device. A contact window is formed at a position in the dielectric layer corresponding to the first metal conductive line. Then, a metal plug is formed in the contact window. The metal plug is used as a mask for etching the semiconductor device, such that the etched semiconductor device takes the form of a shape corresponding to the metal plug. Through the manufacturing method, the semiconductor device is formed according to the shape of the metal plug and is completely aligned with the metal plug.

Method for manufacturing a semiconductor device, method for manufacturing magnetic memory, and the magnetic memory thereof

A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered.

Method for fabricating semiconductor device to lower source/drain sheet resistance

A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Method of fabricating a cylindrical capacitor

A method for forming interconnection plugs comprising the steps of providing a substrate having a dielectric layer formed thereon, wherein an opening exposing a pad area for connection with other structures is also formed in the dielectric layer. Next, a glue layer is formed over the pad area and the dielectric sidewalls of the opening. Subsequently, plug material is deposited into the opening forming a plug layer. This is followed by etching back the plug layer to return the plug material inside the opening to a level below the height of the dielectric layer. Then, a selective etching method having a high selectivity ratio between the dielectric layer and the plug layer is used to etch the dielectric layer. Finally, the dielectric layer and the plug layer are etched to almost the same level of height. The characteristic of this invention is the utilization of the higher etching r!ate of dielectric material with respect to the plug material so that the dielectric layer is etched back to the same level of height as the plug layer. Hence, the formation of recesses on the plug surface and the surface of subsequently deposited metallic layer is avoided.

Method for manufacturing interconnecting plug

A method for forming interconnection plugs comprising the steps of providing a substrate, then forming a dielectric layer having an opening that exposes a pad area for connection with other structures. Next, a glue layer is formed lining the opening and the dielectric layer. Subsequently, plug material is deposited into the opening to form a plug layer. This is followed by etching back the plug layer to a level higher than the glue layer that formed on the top of the dielectric layer. Thereafter, a metallic layer is formed over the plug layer, and a photoresist layer is then coated over the metallic layer. The metallic layer and the plug layer are then patterned by etching such that the plug layer is turned a plug. The characteristic of this invention lies in retaining a portion of the plug layer after the first etching such that the etched plug layer is at a level higher than the glue layer. Through combining the patterning of the metallic layer and the plug layer, one etching step is saved, moreover, recess formation can be prevented, thereby leading to no deterioration of electrical properties or lowering of the yield in the semiconductor devices.

Growing community of inventors

Hsinchu, Taiwan

Ching-Yuan Ho