Vanguard International Semiconductor Corporation

Industrial Technology Research Institute

A.u. Vista Inc.

Au Optronics Corporation

Coretronic Corporation

Ching-Yi Hsu

Chih-Cherng Liao

Pi-Kuang Chuang

Yun-Chou Wei

Yu-Sheng Huang

Po-Sheng Hu

Chien-Hung Chen

Jun-Wei Chen

Chen-Hua Chu

Chih-Wei Lin

Yung-Hsiang Chen

Yi-Pai Huang

Shao-Chang Huang

Pin-Miao Liu

Chia-Hao Lee

Yeh-Ning Jou

Manoj Kumar

Chih-Hung Ting

Chieh-Yao Chuang

Farhang F Shadman

Yu-Chen Wu

Yu-Lung Chin

Hsien-Feng Liao

Kuan-Hsun Chen

Shih-Hao Liu

Wu-Hsi Lu

Kon-Tsu Kin

Wen-Chung Chen

Meng-Shun Huang

Yung-Lung Chou

Wei-Min Cho

Ting-Yu Chang

Jen-Chung Lou

Chiou-Mei Chen

Yen-Shih Ho

Leuh Fang

Ya-Han Liang

Chung-Te Chou

Che-Hua Chang

Pao-Hao Chiu

Tse-Hsiao Liu

Shin-Hao Liu

Cheng-Lun Cho

Che-Hsuan Yang

Meng-Chun Huang

Hsing-Yi Hsieh

Hong-Sian Chi

Chang-He Liu

Ke-Fang Hsu

Chin-Hsiu Huang

Nai-Lun Cheng

A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.

Semiconductor structure with a gate and a shielding structure

A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.

Structure of transferring dies for use in mass transferring process

A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.

Display system and method for forming an output buffer of a source driver

A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.

Semiconductor structure and method for forming the same

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.

Semiconductor structures and fabrication method thereof

A display device is provided. The display device includes a data signal transmitter and a display panel. The data signal transmitter is used to transmit data signals. A display area of the display panel is divided into sub-display areas. Each sub-display area includes light emitting diodes, a data line, column switches, and row switches. A portion of the data line is formed as a data induction coil to receive one of the data signals by wireless sensing. The display panel selects one of the light emitting diodes as a selected light emitting diode by the column switches and the row switches. The selected light emitting diode is coupled to the data line to form a closed loop. The closed loop generates an induced current according to the data signal and causes the selected light emitting diode to emit light according to the induced current.

Display device

A display panel includes a pixel structure corresponding to a display area, and a receiver antenna structure disposed on the pixel structure. The receiver antenna structure includes multiple receiver antennas providing first signals to the pixels of the pixel structure. Each receiver antenna corresponds to at least one pixel, and has an induced decibel (dB). For each receiver antenna, the induced dB is determined by multiple parameters of the receiver antenna, such as a winding number of the receiver antenna; an outer diameter of the receiver antenna; an inner diameter of the receiver antenna; a line pitch of the receiver antenna; a line width of the receiver antenna; and a line thickness of the receiver antenna. The induced dB of at least one of the receiver antennas is greater than the induced dB of other receiver antennas. The display panel may be used in a tiled micro LED display apparatus.

Display panel and display device using the same for wireless signal transmission

A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.

Semiconductor device and method for manufacturing the same

A display panel includes a pixel structure, a receiver antenna structure and a transmitter antenna structure. The pixel structure includes multiple pixels arranged in an array. The receiver antenna structure provides first signals to the pixels, and includes multiple receiver antennas. Each receiver antenna has a resonance frequency. The transmitter antenna structure transmits wireless signals to the receiver antenna structure such that the receiver antenna structure generates the first signals, and includes multiple transmitter antennas. Each transmitter antenna one-to-one corresponds to one receiver antenna and has an identical resonance frequency. The receiver and transmitter antennas are correspondingly divided into multiple receiver and transmitter antenna loop groups, and each antenna loop group includes at least 3 antennas. The resonance frequencies of the receiver antennas of each receiver antenna loop group, in a sequence from an outermost receiver antenna toward an innermost receiver antenna, are not gradually increasing or gradually decreasing.

Wireless display panel with multi-channel data transmission and display device using the same

A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.

Methods for forming the isolation structure of the semiconductor device and semiconductor devices

A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure.

Methods for fabricating trench isolation structure

A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.

Semiconductor structure and method for manufacturing the same

A high voltage (HV) semiconductor device includes: a semiconductor substrate having a first conductivity type; a gate structure disposed over a portion of the semiconductor substrate; a pair of spacers respectively disposed over a sidewall of the gate structure, wherein one of the spacers is a composite spacer comprising a first insulating spacer contacting the gate structure, a dummy gate structure, and a second insulating spacer; a first drift region disposed in a portion of the semiconductor, underlying a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite to the first conductivity type; and a pair of doping regions, respectively disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, wherein the pair of doping regions include the second conductivity type and one of the doping regions is disposed in the first drift region.

High voltage semiconductor device and method for fabricating the same

A backlight module has a light guide plate, a notch structure, a light absorption layer, and at least one light source. The light guide plate has a light-emitting surface and at least one side surface forming an angle with the light-emitting surface. The notch structure is continuously formed on the side surface and concave towards the inside of the light guide plate. The light absorption layer is distributed on an area substantially overlapping the notch structure, and the light source is stored in the notch structure.

Backlight module

Growing community of inventors

Hsinchu, Taiwan

Ching-Yi Hsu