Texas Instruments Corporation

Ching-Te Lin

Jiong-Ping Lu

Phillip D Matz

Sopa Chevacharoenkul

Basab Chatterjee

Kenneth Joseph Newton

Ju-Ai Ruan

Anand J Reddy

A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Reduction of punch-thru defects in damascene processing

Two barrier layers are used for a via or contact. A thin CVD barrier ( ) (e.g., SiN, TiSiN, TaSiN, etc.) is deposited over a structure including within a via or contact hole ( ). A sputter etch is then performed to remove the CVD barrier ( ) at the bottom of the via/contact. A second barrier ( ) is deposited after the sputter etch. The second barrier ( ) comprises a lower resistivity barrier such as Ta, Ti, Mo, W, TaN, WN, MoN or TiN since the second barrier remains at the bottom of the via or contact. A metal fill process can then be performed.

Reliable interconnects with low via/contact resistance

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Plano, TX, United States of America

Ching-Te Lin