Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Ching-Pei Hsieh

Shih-Chang Liu

Chern-Yow Hsu

Chia-Shiung Tsai

Fu-Ting Sung

Chung-Yen Chou

Yu-Wen Liao

Hsia-Wei Chen

Wen-Ting Chu

Kuo-Chi Tu

Chih-Yang Chang

Chin-Chieh Yang

I-Chih Chen

Sheng-Lin Hsieh

Kuan Jung Chen

Yu-Hsing Chang

A method of forming a semiconductor device structure includes forming a first resist structure over a hard mask. The method further includes patterning the first resist structure to form a trench therein. The method further includes performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench. The method further includes patterning the hard mask using the patterned resist structure as an etch mask. The method further includes forming a second resist structure over the patterned hard mask. The method further includes patterning the second resist structure to form an opening therein. The method further includes performing a second hydrogen plasma treatment to the patterned second resist structure. The method further includes patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

Trench etching process for photoresist line roughness improvement

A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Memory cell having resistance variable film and method of making the same

A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Resistance variable memory structure and method of forming the same

A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.

Memory device and method for fabricating the same

A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode.

Semiconductor device and manufacturing method thereof

The present disclosure provides a manufacturing method for the semiconductor structure, including forming a bottom metal layer including copper, forming a planar memory layer over the bottom metal layer, forming an electrode over the planar memory layer by a self-aligning operation, and defining a memory cell by patterning the planar memory layer.

Manufacturing method of semiconductor structure

The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.

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Kaohsiung, Taiwan

Ching-Pei Hsieh