Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Ming Tsai

Yi-Chen Chen

Ray-Ting Chang

Chii-Ping Chen

Wen-Chen Chien

A method of polishing a metal layer comprising the following steps. A structure having an upper patterned dielectric layer with an opening therein is provided. A barrier layer is formed over the patterned upper dielectric layer and lining the opening. A metal layer is formed over the barrier layer, filling the opening. A first polish step employing a first slurry composition is conducted to remove a portion of the overlying metal layer. A second polish step employing the first slurry composition is conducted to: polish the partially removed overlying metal layer; and to expose portions of the barrier layer overlying the patterned upper dielectric layer. A third polish step employing a second slurry composition is conducted to remove the exposed barrier layer portions and exposing underlying portions of the patterned upper dielectric layer. A fourth polish step employing the second slurry composition and BTA is conducted to buff the exposed upper dielectric layer portions.

Barrier-slurry-free copper CMP process

A method for achieving a predetermined electrical resistance of a semiconductor device metal line in a CMP process including providing a semiconductor process wafer comprising at least one dielectric layer for etching an opening through a thickness of the at least one dielectric layer; measuring a thickness of the at least one dielectric layer prior to etching the opening; etching the opening through a thickness of the at least one dielectric layer; measuring at least one dimension of the opening from which at least an opening depth is determined; forming a metal layer to fill the opening; and, performing a chemical mechanical polish (CMP) process to remove at least the metal layer overlying the opening level to form a metal filled opening according to a projected metal filled opening electrical resistance.

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Miaoli, Taiwan

Ching-Ming Tsai