United Microelectronics Corp.

United Semiconductor Corp.

Ching-Hsing Hsieh

Min-Hsian Chen

Feng-Chi Chung

Yi-Chun Lin

Chih-Ching Hsu

Shuenn-Jeng Chen

William Lu

Chia-Chi Chang

Chien-Chuan Yu

Jy-Hwang Lin

Chia-Chieh Yu

Yueh-Feng Ho

Tsung-Yuan Hung

Lian-Hua Shih

Chen-Chih Tsai

Chen-Hui Huang

Yung-Yu Yang

Ju-Te Chen

Jiunn Hsien Lin

Tzu-Ping Kao

Cheng-Hsien Chen

Chiu-Ping Chang

Ming-Tung Wang

Meng-Chih Chang

Li-Ting Lin

Chi-Cheng Yang

Yung-Chieh Kuo

Chin-Ching Hsu

An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.

Automatic detecting method and automatic detecting apparatus using the same

A virtual metrology system at least includes a process apparatus including a set of process data, the process apparatus producing a workpiece according to the set of process data. A virtual metrology server is configured to gather the set of process data, cluster the set of process data to obtain data clusters, and compare the data clusters with patterns. If the data clusters meet the patterns corresponding to the data clusters, performing a corresponding maintenance, repair, and overhaul step on the process apparatus.

Virtual metrology system and method

A method of monitoring a processing system for processing a substrate is provided. The method includes the following steps: acquiring data from the processing system for a plurality of parameters, the data including a plurality of data values; grouping the parameters into a plurality of sub-groups, each of the sub-groups including a plurality of correlated parameters; constructing a principle components analysis (PCA) model from the data values for the correlated parameters in a first one of the sub-groups, including normalizing the data values in the first one of the sub-groups with a first weighting factor and a second weighting factor, wherein the first weighting factor is different from the second weighting factor; and determining a statistical quantity using the PCA model.

Method of monitoring processing system for processing substrate

A virtual metrology system and a method therefor are provided herein. In the system, a set of process data is gathered and clustered according to a plurality of predetermined patterns. The clustered set of process data is calculated according to the corresponding pattern, so as to obtain a comparison result. If the obtained result meets a desired output, a corresponding step is performed based on the result. In one case, the corresponding step is a normal sampling step if the clustered set of process data meets the corresponding pattern. If the clustered set of process data does not meet the corresponding pattern, an alarm is generated thereby, and the corresponding equipment may be shut down. In another case, the corresponding step is a maintenance, repair, and overhaul step if the clustered set of process data meets the corresponding pattern.

A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the gate conductor of the MOS transistor.

Semiconductor device structure for reducing hot carrier effect of MOS transistor

Method for reducing hot carrier effect of MOS transistor

A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300&#x2dc;400 degrees centigrade for 10&#x2dc;60 seconds and the second step of the second thermal process is performed at 450&#x2dc;550 degrees centigrade for 10&#x2dc;60 seconds.

Salicide process

A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein the second thermal process includes a first step performed at 600&#x2dc;700 degrees centigrade for 10&#x2dc;60 seconds and a second step performed at 750&#x2dc;850 degrees centigrade for 10&#x2dc;60 seconds. If the metal layer is selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300&#x2dc;400 degrees centigrade for 10&#x2dc;60 seconds and the second step of the second thermal process is performed at 450&#x2dc;550 degrees centigrade for 10&#x2dc;60 seconds.

An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the conductive line. A second dielectric layer is formed on the first dielectric layer by a spin-on glass method. A curing treatment with an electron beam having a low energy and a high dosage is performed to cure an upper portion of the second dielectric layer so that a cured third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the cured third dielectric layer. A chemical-mechanical polishing process is performed using the cured dielectric layer as a stop layer. A cap layer is formed on the fourth dielectric layer.

Method for forming inter-metal dielectrics

This invention provides a planarization method that solves the microscratch problem caused by chemical-mechanical polishing. This method comprises the following steps: providing a substrate with semiconductor devices, forming a SRO oxide on the substrate, forming a SOG layer on the SRO layer, performing a curing process, performing an implantation process during the curing process, forming an oxide layer on the SRO oxide, and planarizing the oxide layer by CMP. Another SOG layer is formed on the planarized oxide layer, a curing process is performed on the second SOG layer, and a cap oxide layer is formed on the second SOG layer to adjust the thickness of the dielectric layer. This invention can solve conventional problems such as microscratching and metal bridges.

Planarization process

The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer. A metal layer is formed to fill the via hole by chemical vapor deposition.

Method of manufacturing interconnect

A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For each different etching mass, the TiN etching mask is not necessarily removed after etching; the silicon nitride etching mask is removed after etching; the oxide layer in the oxide/TiN etching mask is sacrificial layer.

Method for fabricating a via

A method of forming a via is provided comprising a plasma treatment at the spin-on-glass layer after forming the unlanding via. The plasma comprises hydrogen and a second gas. The mist containing in the spin-on-glass layer is damaged and removed away.

Method of forming a via with plasma treatment of SOG

A method of forming a contact via includes forming a wiring, a first insulator layer, and a spin-on glass layer, respectively, over a semiconductor substrate. Fluorine ions are implanted into the spin-on glass layer. A second insulator layer is formed over the spin-on glass layer. The wiring is exposed by patterning the second insulator layer, the spin-on glass layer, and the first insulator layer, respectively.

Growing community of inventors

Hsinchu County, Taiwan

Ching-Hsing Hsieh