Advanced Semiconductor Engineering, Inc.

Ching-Fu Horng

Yung-Hui Wang

Chun-Hung Lin

Su Tao

Ho-Ming Tong

Jen-Kuang Fang

Chun-Chi Lee

Yung-Chi Lee

Tsung-Hua Wu

Yu-Chen Chou

Shih-Kuang Chen

Shyh-Ing Wu

A manufacturing method of a multi-layer circuit board embedded with a passive component includes the steps of: providing a conductive foil which has one or more pairs of metal protruding points; connecting a passive element to the corresponding metal protruding points; providing a board having a core substrate with organic insulation layer on a core substrate; stacking the conductive foil and the board, wherein the passive component is embedded in the organic insulation layer and patterning on the conductive foil.

Manufacturing method of a multi-layer circuit board embedded with a passive component

A circuit carrier including a core layer, a passive component, a plurality of dielectric layers, and a plurality of circuit layers is provided. The core layer has a first surface and a second surface. In addition, the core layer has a hole, and the passive component is embedded in the hole of the core layer. Furthermore, the circuit layers and the dielectric layers are alternately disposed on the first surface and the second surface of the core layer respectively. The dielectric layers have a plurality of conductive vias, and at least one of the circuit layers is electrically connected to the passive component through the conductive vias. As described above, the electrical performance of the circuit carrier is enhanced. Furthermore, a manufacturing process of the circuit carrier mentioned above is also provided.

Circuit carrier and manufacturing process thereof

A method of forming a plurality of bumps over a wafer mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming an adhesive layer on the surface of the wafer to cover the bonding pads, patterning the adhesive layer to expose the bonding pads to form a patterned adhesive layer, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer, and reflowing the bumps.

Bumping process

A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer, which exposes the bonding pads, is provided. Next, a first dielectric layer is disposed on the wafer so as to form a plurality of first openings and second openings. The first openings and the second openings expose the bonding pads and the passivation layer respectively. Afterward, a patterned first electrically conductive layer is formed on the first dielectric layer, the bonding pads and the passivation layer exposed out of the first dielectric layer through the second openings. Then, a second patterned conductive layer is formed directly on the first patterned conductive layer. Next, a second dielectric layer is formed on the first dielectric layer and the patterned second electrically conductive layer, and exposes portions of the second patterned layer through the second openings so that the exposed portion of the second patterned layer through the second openings are regarded as a plurality of bump pads. Therein, the bump pads are electrically connected to the bonding pads through the patterned first electrically conductive layer and the patterned second electrically conductive layers. Finally, a plurality of bumps are formed on the bump pads and the bumps are then reflowed to be mounted securely on the bump pads.

A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.

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Kaohsiung, Taiwan

Ching-Fu Horng