National Science Council

Other

National Yang Ming Chiao Tung University

Industrial Technology Research Institute

Ching-Fa Yeh

Yueh-Chuan Lee

Kwo-Hau Wu

Tien-Fu Chen

Jen-Chung Lou

Shuo-Cheng Wang

Yuh-Ching Su

Chih-Chuan Hsu

Muh-Wang Liang

Jen-Rong Huang

Jiann-Shiun Kao

Pang-Min Chiang

Jyh-Nan Jeng

Tso-Hung Fan

Shyue S Lin

Jwinn Lein Su

Chen Max

Chien-Hsing Lin

Tai-Ju Chen

Jeng-Shu Liu

The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).

Method for fabrication of polycrystalline silicon thin film transistors

A method for fabricating polycrystalline silicon film transistors, which includes a polysilicon spacer capping onto a sidewall of an active layer in the thin film transistors by an isotropic dry etching of the silicon film. This method suppresses the shrinkage of the active layer during recrystallization by the laser. Large grains are formed in the channel after recrystallization utilizing a high-energy continuous wavelength laser or an excimer laser annealing the active layer. This process does not require an additional mask. Uniform arrangement of grain boundaries and large grain sizes promotes uniformity of performance of the device, which is important in the fields of low temperature polycrystalline silicon thin film transistors (LTPS-TFTs).

Method for fabrication of polycrystallin silicon thin film transistors

The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure

A method for liquid phase deposition, including the steps of providing at least two raw materials from at least two supply devices of a saturation reaction system into a mixture trough and stirring until saturation occurs, filtering out unnecessary solid-state particles, and providing saturated and filtered liquid into an over-saturation reaction trough of a steady-flow over-saturation loop reaction system and stopping the saturated and filtered liquid when the over-saturation reaction trough is filled and the saturated and filtered liquid over-flows into a liquid level control trough to a pre-determined level. The method also includes the steps of providing a substrate in the over-saturation reaction trough, providing reactants from at least two supply devices into the over-saturation reaction trough, and depositing a thin film onto the substrate when the saturated liquid becomes over-saturated.

Method for liquid phase deposition

The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.

Process for preparing Cu damascene interconnection

The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.

Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method

A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.

Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition

A method of making a polysilicon thin-film transistor is presented. Device characteristics are improved when a silicon dioxide capping layer is formed by an ion plating method.

Method of making a TFT having an ion plated silicon dioxide capping layer

The present invention relates to a method for forming a polyoxide film on a doped polysilicon layer, which is suitable for use as an inter-polysilicon polyoxide film between a doped polysilicon floating gate and a doped polysilicon control gate. The method includes conducting an electrolytic reaction at a room, temperature such that a polyoxide layer is formed on a doped polysilicon layer acting as an anode. The polyoxide layer is preferably further subjected with a rapid thermal processing to improve its electrical characteristics.

Method for forming a polyoxide film on doped polysilicon by anodization

A method is capable of providing a semiconductor device with a gate having thereon a thicker silicide or metal layer and further having a lower interconnect resistance. The method is further capable of providing the semiconductor device with a polysilicon gate having a recessed tungsten structure for prevention of short circuit between the gate and the drain or the source. For forming a grooved gate structure, a photo-resist is formed on the polysilicon gate before growing on the entire surface of the silicon substrate a silicon dioxide layer. The silicon dioxide layer and the thin gate oxidation layer on drain/source are etched vertically by a reactive ion etching until the photo-resist and the silicon surface of drain/source are exposed. A plurality of spacers are thus formed on the side walls of the photo-resist/polysilicon gate. Upon stripping the photo-resist, the grooved gate structure is formed on the semiconductor device.

Method of making a grooved gate structure of semiconductor device

A polysilicon transistor having a buried-gate structure is fabricated by a method involving a liquid phase deposition which is used for depositing selectively a silicon dioxide layer on a polysilicon layer, but not on a photoresist layer. The silicon dioxide liquid phase deposition is brought about by using an aqueous hydrofluorosilicic acid (H.sub.2 SiF.sub.6) solution supersaturated with silicon dioxide. Upon completion of the stripping of the photoresist layer, the selectively-deposited silicon dioxide layer is used as a mask to perform the source/drain ion implant.

Method for fabricating a polysilicon transistor having a buried-gate

A liquid phase deposition method involves a reaction mixture composed of a hydrosilicofluoric acid aqueous solution supersaturated with silicon dioxide, and a semiconductor substrate disposed therein. The reaction mixture is treated with an ultrasonic oscillation at a frequency ranging between 20 and 100 KHz and at a temperature ranging between 10.degree. and 50.degree. C. for accelerating the growth rate of a silicon dioxide layer formed on the semiconductor substrate.

Method for enhancing the growth rate of a silicon dioxide layer grown by

A silicon dioxide layer grown by liquid phase deposition is, subjected to an oxygen or hydrogen plasma treatment to enhance the physical and electrical properties thereof. The plasma treatment is carried out at a temperature of about 300.degree. C.

Growing community of inventors

Hsinchu, Taiwan

Ching-Fa Yeh