Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Chung Pai

Jyh-Huei Chen

Yu-Hsien Lin

Jung-Tzu Hsu

Chia-Shiung Tsai

Yuan-Chih Hsieh

Ming-Chyi Liu

Hua-Shu Ivan Wu

Gwo-Yuh Shiau

Kai-Chih Liang

Tsung-Mu Lai

Fa-Yuan Chang

Nick Y M Shen

Chin-Hsiang Ho

Chu-Wei Cheng

A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step.

Method of fabricating an integrated circuit device having backside bevel protection

The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Backside bevel protection

The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Process for wafer bonding

Growing community of inventors

Taipei, Taiwan

Ching-Chung Pai