Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Te Wang

Hsien-Wei Chen

Wei-Cheng Wu

Chen-Hua Douglas Yu

Tsung-Shu Lin

Chien-Chia Chiu

Meng-Tsan Lee

Cheng-Hsien Hsieh

Li-Han Hsu

Yan-Fu Lin

Tzu-Shiun Sheu

A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

Routing design of dummy metal cap and redistribution line

A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

Integrated fan-out package, semiconductor device, and method of fabricating the same

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Taipei, Taiwan

Chin-Te Wang