Intel Corporation

Chin Lee Kuan

Amit Kumar Jain

Sameer Shekhar

Bok Eng Cheah

Jackson Chung Peng Kong

Khang Choong Yong

Min Suet Lim

Jenny Shio Yin Ong

Tin Poay Chuah

Stephen H Hall

Ramaswamy Parthasarathy

Raymond Chong

Eng Huat Goh

Seok Ling Lim

Dong-Ho Han

Howe Yin Loo

Kevin Joseph Doran

Kaladhar Radhakrishnan

Jiun Hann Sir

Jonathan P Douglas

Michael Zelikson

Hoay Tien Teoh

Mooi Ling Chang

Alexander Waizman

Siew Fong Yap

An apparatus, system, and method for improved thermal design power (TDP) range are provided. A device includes a first voltage regulator configured to provide first voltage of a first voltage value, a second voltage regulator configured to provide a second voltage of a second, different voltage value, a first capacitor electrically coupled between a first output of the first voltage regulator and a ground, a second capacitor electrically coupled between a second output of the second voltage regulator and the ground, a first switch electrically coupled between the first output and the second output, a second switch situated in parallel with the first switch, the second switch electrically coupled between the first output and the second output, and a controller configured to provide control signals that control the first voltage regulator, the second voltage regulator, the first switch, and the second switch.

Platform voltage regulator circuitry configurations

The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

Hybrid boards with embedded planes

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

Embedded bridge substrate having an integral device

A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Vertical embedded component in a printed circuit board blind hole

According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

Stacked semiconductor package and method of forming the same

A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

3D trench reference planes for integrated-circuit die packages

A multiple-damascene structure is located below a semiconductor device footprint on a printed wiring board, where the structure includes multiple recesses that containing useful devices coupled to a semiconductive device.

Stacked-component placement in multiple-damascene printed wiring boards for semiconductor package substrates

A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.

Stepped interposer for stacked chip package

A capacitor loop substrate assembly includes a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects are formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

Method of forming a capacitive loop substrate assembly

Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.

Magnetic sensing scheme for voltage regulator circuit

Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard

Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.

Shield to protect vias from electromagnetic interference

An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Apparatus, system, and method for reducing voltage overshoot in voltage regulators

An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Crystal oscillator interconnect architecture with noise immunity

An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

Growing community of inventors

Bayan Lepas, Malaysia

Chin Lee Kuan