Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Hua Wang

Shin-Puu Jeng

Po-Yao Lin

Shu-Shen Yeh

Yu-Sheng Lin

Po-Chen Lai

Ming-Chih Yew

Chia-Kuei Hsu

Che-Chia Yang

Kuang-Chun Lee

Tsung-Yen Lee

Shyue-Ter Leu

Feng-Cheng Hsu

Li-Ling Liao

Wen-Yi Lin

Shuo-Mao Chen

Chia-Hsiang Lin

Chien-Hung Chen

Cheng-Lin Huang

Hsiu-Mei Yu

Yu-Huan Chen

Yi-Hang Lin

Chun-Wei Chen

Chien Hung Chen

Chien-Shen Chen

Chien-Tung Yu

Yu Chen Lee

Shin-Puu Zeng

Ping-Tai Chen

Yi Hang Lin

Chia Kuei Hsu

Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Semiconductor device and method of manufacture

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Integrated circuit package and method of forming same

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.

Method for forming chip package structure

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.

Chip package structure with lid

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Multi-chip device and method of formation

A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.

Manufacturing method of semiconductor package

In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.

Package and method for forming the same

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.

Chip package structure with ring dam

A semiconductor device package is provided, including a substrate, a semiconductor device, a ring structure, a lid structure, and at least one adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The ring structure comprises a first ring part and a second ring part on opposite sides of the semiconductor device. A first gap is formed between the first ring part and the semiconductor device, a second gap is formed between the second ring part and the semiconductor device, and the first gap is smaller than the second gap. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in the first gap and configured to connect the lid structure and the first surface of the substrate.

Semiconductor device package with stress reduction design

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure and a second chip structure over the wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The chip package structure includes a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Chip package structure with ring structure

A method of forming a semiconductor package structure is provided. The method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. The interposer substrate is disposed between the carrier substrate and the first semiconductor device. The lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.

Method for forming semiconductor package structure

A package assembly includes a package substrate, a solder resist layer on the package substrate and including an elongated solder resist opening, and an interposer module on the package substrate and including a corner located on the elongated solder resist opening.

Package assembly including package substrate with elongated solder resist opening and methods for forming the same

A semiconductor die package is provided, including a package substrate, and two semiconductor dies disposed over the package substrate and arranged in a first direction. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. The ring structure includes a first part having a first height and a second part recessed from the bottom surface and having a second height lower than the first height. The first part includes multiple higher parts arranged side by side in at least some of side areas of the ring structure, and the second part includes multiple lower parts between the higher parts. The lower parts include multiple first lower parts arranged in multiple corner areas of the ring structure and multiple second lower parts arranged in opposite side areas of the ring structure extending in the first direction.

Semiconductor die package with ring structure

A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Semiconductor package

A semiconductor package includes a die, a first conductive pattern, a second conductive pattern and first and second under-ball metallurgy (UBM) patterns. The first conductive pattern and the second conductive pattern are disposed below and electrically connected to the die, wherein the first conductive pattern has an ellipse-like shape, and the second conductive pattern has a circular shape. The first and second under-ball metallurgy (UBM) patterns correspond to the first and second conductive patterns, the first conductive pattern has a first length, the second conductive pattern has a second length, the first and second UBM patterns have a third length, wherein the first length is larger than the third length and the second length is smaller than the third length.

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Taipei, Taiwan

Chin-Hua Wang