United Microelectronics Corp.

Chin-Fu Lin

Chun-Yuan Wu

Chih-Chien Liu

Chin-Cheng Chien

Chi-Mao Hsu

Hsin-Fu Huang

Teng-Chun Tsai

Min-Chuan Tsai

Tsun-Min Cheng

Chien-Hao Chen

Wei-Yu Chen

Chia-Lin Hsu

Kun-Hsien Lin

Chun-Ling Lin

Kuo-Chih Lai

Nien-Ting Ho

Wei Chen

Chien-Ting Lin

Hui-Lin Wang

Shih-Hung Tsai

Yen-Chen Chen

Chun-Yao Yang

Yi-Syun Chou

Chi-Yuan Sun

Bin-Siang Tsai

Yu-Ru Yang

Shih-Min Chou

Chun-Hung Chen

Po-Chun Chen

Yao-Hung Liu

Tzung-Ying Lee

Hsin-Kuo Hsu

Ming-Chang Lu

Hai Tao Liu

Ya-Hsueh Hsieh

Shouguo Zhang

Yen-Liang Lu

Ming Hua Du

Xiao Wu

Yu-Cheng Tung

Yi-Wei Chen

Ssu-I Fu

Chun-Hsien Lin

Chien-Chung Huang

Hsin-Yu Chen

Hung-Lin Shih

Wen-Tai Chiang

Hsiao-Pang Chou

Ai-Sen Liu

Ying-Tsung Chen

Hon-Huei Liu

Wei-Ming Hsiao

Ko-Wei Lin

Huei-Ru Tsai

Min-Hsien Chen

Szu-Yao Yu

Jia-Jia Chen

Ching-Wei Hsu

Yuan-Cheng Yang

Chi-Ray Tsai

Jing-Gang Li

Hui-Ting Lin

Jian-Hong Su

Hsien-Che Teng

Cheng-Hsien Chou

Chan-Lon Yang

Shih-Fang Tzou

Chung-Yi Chiu

Ping-Chia Shih

Tzyy-Ming Cheng

Chien-Ming Lai

Chih-Hao Yu

Zhi-Cheng Lee

Che-Hua Hsu

Hui-Shen Shih

Yi-Wen Chen

Chun-Hung Cheng

Yu-Ying Lin

Jei-Ming Chen

Wei-Chuan Tsai

Yau-Kae Sheu

Tong-Jyun Huang

Ted Ming-Lang Guo

Chun-Sung Huang

Yang-Ju Lu

Yu-Chieh Lin

Ya-Jyuan Hung

Jen-Po Huang

Kuan-Hsien Li

Seng Wah Liau

Xu Yang Shen

Liang-An Huang

Chung-Che Huang

Chia-Fu Cheng

Yu-Chun Huang

Hsin-Liang Liu

Yu-Cheng Wang

Shih-Feng Su

Yi-Ting Liao

Yu-Ciao Lin

A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Magnetic tunnel junction (MTJ) device and forming method thereof

A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Semiconductor device

The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

Semiconductor structure with an epitaxial layer

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

ReRAM structure and method of fabricating the same

Semiconductor device and method for fabricating the same

The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along &#x3c;&#x3e; crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.

Method of manufacturing semiconductor structure with an epitaxial layer

An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

Integrated circuit device and method of fabricating integrated circuit

A non-volatile memory includes a back gate, a first graphene ribbon layer, a dielectric layer, a second graphene ribbon layer and a porous dielectric layer. The back gate is disposed in a substrate. The first graphene ribbon layer is disposed on the substrate. The dielectric layer covers the first graphene ribbon layer but exposes an exposed part of the first graphene ribbon layer. The second graphene ribbon layer including two end parts connected by a cantilever part is disposed above the first graphene ribbon layer, and the cantilever part is right above the exposed part of the first graphene ribbon layer. The porous dielectric layer is disposed on the dielectric layer and seals the cantilever part. The present invention also provides a method of forming said non-volatile memory.

Non-volatile memory and forming method thereof

An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Epitaxial process applying light illumination

An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Electrical chemical plating process

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

Semiconductor device and method for forming the same

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Tainan, Taiwan

Chin-Fu Lin