Vlsi Technology, Inc.

Chin-Ching Huang

Ahmad B Hamzehdoost

Sang S Lee

Ramachandra A Rao

Fernand N Forcier, Jr

Ronald J Molnar

Kenny Y Ng

Elizabeth C Galindo

A method for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.

Printed circuit board layout to minimize the clock delay caused by

A printed circuit board layout is provided for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.

A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference. On one of the ledges, contact fingers corresponding to a first set of input/output signals are evenly dispersed around contact fingers corresponding to the ground reference, and on another one of the ledges, contact fingers corresponding to a second set of input/output signals are evenly dispersed around contact fingers corresponding to the voltage supply. On a bottom surface of the integrated circuit package a plurality of pins are arranged in a pin-grid-array, and pins corresponding to the voltage supply and ground reference are placed in the four outer corners of the bottom surface, so as to minimize parasitic noise generated on the voltage and ground lines connected to these pins, by active circuitry of the packaged integrated circuit.

Multi-layered, integrated circuit package having reduced parasitic noise

A multi-layer package for semiconductor dies using two different types of dielectric materials improves the performance of a semiconductor package. The first material having a high dielectric constant is placed between the power and ground planes to form a decoupling capacitor and the second material having a low dielectric constant is used to contact the signal traces. Silicon carbide is preferred for the high dielectric constant material.

High performance package using high dielectric constant materials for

A package assembly for an integrated circuit die includes a base having a cavity formed therein for receiving an integrated circuit die. The base has a ground-reference conductor. A number of bonding wires are each connected between respective die-bonding pads on the integrated circuit die and corresponding bonding pads formed on the base. The lid has an electrically conductive layer formed on it to cover the integrated circuit die in the cavity formed in the base. The electrically conductive layer formed on the lid is positioned in close proximity to some of the plurality of bonding wires. The electrically conductive layer formed on the lid is connected to the ground-reference conductor of the base. This arrangement reduces both the self-inductances of the one or more conductors and the mutual inductance between the one or more conductors. With this arrangement the electrically conductive layer formed on the lid is grounded to reduce interference being radiated from the electrically conductive layer.

Package structure and method for reducing bond wire inductance

A thermal test apparatus for measuring the thermal heat transfer characteristics of semiconductor packaging material as well as the thermal characteristics of the package design is disclosed comprising a substrate having the size and shape of a semiconductor die. The substrate is in contact with the semiconductor packaging material. A heating source for heating the substrate is located within the apparatus, along with a temperature sensitive element for which the voltage drop across the element is a function of temperature. The element is connected in series via a first set of conductive traces to forcing pads used to force current through the element. Sensing pads for measuring the forward voltage drop of the diode are connected in parallel via a second set of conductive traces across the element to two points very close to the element in order to greatly reduce the thermal resistance measurement error due to the resistance in the conductive trace material. In another aspect of the present invention the thermal measurement error is reduced by connecting the sensing pads via a second set of conductive traces to two points across the diode such that those two points are located not more than two microns from the diode. Once the voltage drop across the element is measured, the temperature of the element and the junction surrounding the element can be determined and standardized to indicate the relative thermal conductive properties of the various semiconductor designs and packaging materials used.

Technique for measuring thermal resistance of semiconductor packages and

An Au/Si die attach method for attaching a die to a package including preheating the package, melting Au/Si preform in the package cavity, scratching the die onto the package cavity to form a die attach bond, and gradually cooling an Au/Si die bond by reducing heat supplied the package, so as to cool the package through a monotonically decreasing sequence of temperatures, where the package is maintained for a predetermined period of time at each temperature in the sequence. A heating block with segments supplies a decreasing amount of heat to the packages to let the die attach bond gradually cool. The packages are kept on top of the segments of the heating block for a predetermined period of time and each segment is heated to a specific temperature. The gradual cooling of the die attach bond decreases the thermal resistance and prevents the creation of voids in the die attach bond.

Apparatus for bonding a semiconductor die to a package using a

An Au/si die attach method for attaching a die to a package including preheating the package, melting an Au/Si preform in the package cavity, scratching the die onto the package cavity to form a die attach bond, and gradually cooling an Au/Si die bond by reducing heat supplied to the package, so as to cool the package through a monotonically decreasing sequence of temperatures, wherein the package is maintained for a predetermined period of time at each temperature in the sequence. A heating block with segments supplies a decreasing amount of heat to the packages to let the die attached bond gradually cool. The packages are kept on top of the segments of the heating block for a predetermined period of time and each segment is heated to a specific temperature. The gradual cooling of the die attach bond decreases the thermal resistance and prevents the creation of voids in the die attach bond.

Method of bonding a semiconductor die to a package using a gold/silicon

Where a lead frame or lead structure in a plastic or ceramic-type package is made of a ferromagnetic material, an electrically conducting non-ferromagnetic material is added to create a low-inductance path between a semiconductor die and the terminals of the package to reduce self-inductance in the package. To provide an effective low-inductance current path to the ferromagnetic lead frame, the cross-sectional dimensions of the non-ferromagnetic path is preferably no less than 50 microinches. Where the lead frame or lead structure is made from an electrically conducting non-ferromagnetic material, a ferromagnetic material is added to provide strength and rigidity to the lead frame or lead structure. The material added may be plated, spot plated, or cladded onto the starting material. The leads or terminals of a socket may be also be constructed in a similar manner to improve its wear-resistance and rigidity while maintaining a low self-inductance.

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San Jose, CA, United States of America

Chin-Ching Huang