Taiwan Semiconductor Manufacturing Comp. Ltd.

Chii-Ping Chen

Hsiu-Wen Hsueh

Wen-Sheh Huang

Yu-Hsiang Chen

Ya-Ching Tseng

Wan-Te Chen

Cai-Ling Wu

Po-Hsiang Huang

Dian-Hau Chen

Neng-Jye Yang

Jiing-Feng Yang

Chung-Hui Chen

Chih-Hao Chen

Ru-Gun Liu

Wen-Chun Huang

Wei-Chih Chen

Ya-Lien Lee

Ming-Hui Chih

Sheng-Feng Liu

Bi-Ling Lin

An-Jiao Fu

Ming-Chung Liang

Yuh-Jier Mii

Jen Hung Wang

Wei-Ren Wang

Cheng-Kun Tsai

Chih-Ming Lai

Lee-Chung Lu

Tsai-Sheng Gau

Burn Jeng Lin

Cheng-Lin Huang

Ken-Hsien Hsieh

Wen-Hao Chen

Yuan-Te Hou

Hsin-Yi Tsai

Chung-Yi Lin

Shyue-Shyh Lin

Ko-Bin Kao

Chi-Feng Lin

Yung-Shih Cheng

Fang-Yu Fan

Chang-Wen Chen

Yu-Hsiang Kao

Lai Chien Wen

Wen-Chen Chien

Ching-Ming Tsai

Kuo-Hwa Wang

In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

Self-aligned scheme for semiconductor device and method of forming the same

A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

Thermal dissipation in semiconductor devices

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.

Diffusion barrier layer for conductive via to decrease contact resistance

The present disclosure relates a method of forming an integrated chip. The method includes forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate, and forming a second ILD layer over the first ILD layer. The second ILD layer is patterned to form an interconnect opening that exposes the first interconnect. A blocking layer is formed onto the first interconnect. A barrier layer is formed within the interconnect opening and the blocking layer is removed to expose the first interconnect. A second interconnect is formed within the interconnect opening.

Barrier free interface between BEOL interconnects

A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

Method for forming a semiconductor structure by diffusing manganese from a seed layer to a barrier layer

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

Semiconductor devices and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.

Semiconductor device structure with resistive element

A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.

Method for manufacturing semiconductor structure with resistive elements

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first conductive feature and a second conductive feature surrounded by the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element having a first portion over the second dielectric layer and a second portion penetrating through the second dielectric layer to be electrically connected to the first conductive feature. In addition, the semiconductor device structure includes a conductive via penetrating through the second dielectric layer to be electrically connected to the second conductive feature. The second portion of the resistive element is wider than the conductive via.

Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.

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Taichung, Taiwan

Chii-Ping Chen