Taiwan Semiconductor Manufacturing Comp. Ltd.

Chii Ming Wu

Yao-Wen Chang

Tzu-Chung Tsai

Julie Yang

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Growing community of inventors

Taipei, Taiwan

Chii Ming Wu