United Microelectronics Corp.

Chih-Yuan Hsiao

Hua-Chou Tseng

Po-Jau Tsao

Yao-Chin Cheng

Ching-Chiao Hao

A method for forming transistors static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell area and periphery area, wherein the cell area comprises a first P-type region, a second P-type region, a first N-type region and a second N-type region, the periphery area comprises numerous periphery P-type regions and numerous periphery N-type regions; covering the first P-type region, the second P-type region and the periphery P-type regions by a first photoresist; forming numerous N-type sources and numerous N-type drains in the first P-type region, the second P-type region and the periphery P-type regions. Remove the first photoresist. Use a second photoresist to cover the periphery N-type regions and some the N-type drains which are located in both the first N-type region and the second N-type regions; and performing a large angle implanting process to form numerous P-type enlarged drains and numerous P-type region and the P-type second region, wherein numerous P-type extra sources also are formed on outside of some the N-type drains which are located in both the first N-type region and the second N-type region.

Four transistors static-random-access-memory

A four-transistor SRAM cell, which could be viewed as at least including two word line terminals, comprises the following elements: a first word line terminal, a second word line terminal, a first bit line terminal, a second bit line terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is coupled to the first word line terminal and the source of the first transistor is coupled to the first bit line terminal, the gate of the second transistor is coupled to the second word line terminal and the source of the second transistor is coupled to the second bit line terminal, the source of the third transistor is coupled to the drain of the first transistor and the gate of the third transistor is coupled to the drain of the second transistor, the source of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor is coupled to the drain of the first transistor. Significantly, one essential characteristic of the memory cell is that two word line terminals are used to control the state of two independent transistors separately.

Four transistor static-random-access-memory cell

A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor. Significantly, one essentially characteristic of the memory cell is two word line terminals are used to control state of two independent transistors separately.

Four transistors static-random-access-memory cell

A method of fabricating a transistor. A gate structure is formed on a substrate. A spacer is formed on a sidewall of the gate structure. A first doping step is performed with the gate structure and the spacer serving as masks to form a source/drain region in the substrate. A silicide layer is formed on the source/drain region. The spacer is removed. A second doping step is performed with the gate structure serving as a mask to form a lightly doped drain region in the substrate.

Method of fabricating a transistor

The present invention relates to a method of forming a MOS transistor on a semiconductor wafer. A gate is first formed on the silicon substrate of the semiconductor wafer, then a first spacer made of silicon nitride and the LDD are formed adjacent to the gate. A conductive layer is formed on the semiconductor wafer that forms a corner on the conjoining section of the spacer and the silicon substrate. A spacer made of silicon oxide is formed on the corner of the conductive layer,, then an etching process is performed to remove the conductive layer above the gate and the silicon substrate. The conductive layer on the corner adjacent to the first spacer remains. Finally, the spacer made of silicon oxide is completely removed, and an ion implantation process is performed to form a source and drain on the silicon substrate adjacent to the conductive layer.

Method of forming a MOS transistor

A method for forming a gate contact is disclosed. The method includes that a semiconductor substrate and a silicon dioxide layer are provided upon the semiconductor substrate. Then, a polysilicon layer is formed upon the oxide layer. Next, defining and etching the polysilicon layer are carried out to form a gate. Implanting upon the top surface of the silicon dioxide layer is achieved so that source/drain region is formed below and abuts the silicon dioxide layer. The source/drain region will be annealed. A spacer can be formed and abuts the sidewall of the gate. A salicide is formed and overlaps the top surface of the gate and over the semiconductor substrate. Then, a gate contact area can be defined upon the top surface of the semiconductor substrate by using a mask that has a pattern covering approximately half of the gate and the spacer. The half of the spacer can be removed without covering by the mask. Finally, implanting will be completed to form the gate contact in the substrate by using the salicide as an implanting mask.

Method for forming gate contact in complementary metal oxide semiconductor

A method for forming a protection circuit that starts with forming a first-type well and a second-type well on a first-type substrate. By forming isolations, a first active region is defined within the second-type well, and a second active region, a third active region and a fourth active region are defined within the first-type well. A first polysilicon layer is formed on the substrate and patterned to expose the third and the fourth active regions. A second polysilicon layer is formed on the substrate and patterned into a first gate that connects the first and the third active regions, and a second gate that connects the second and the fourth active regions. Then, by performing a first-type implantation process, the first gate is turned into a first-type gate. First-type source/drain regions are formed in the first active region, and first-type contacts are formed in the third active region as well. Similarly, the second gate is turned into a second-type gate, second-type source/drain regions are formed in the second active region, and second-type contacts are formed in the fourth active region by performing a second-type implantation process.

Growing community of inventors

Feng Shan, Taiwan

Chih-Yuan Hsiao