Advanced Semiconductor Engineering, Inc.

Chih-Yi Huang

Chen-Chao Wang

Chih-Pin Hung

Hung-Hsiang Cheng

Keng-Tuan Chang

Teck-Chong Lee

Chang-Lin Yeh

Jen-Chieh Kao

Tsung-Tang Tsai

Fu-Chen Chu

Chi-Tsung Chiu

Chin-Li Kao

William T Chen

Ian Hu

Yung-Shun Chang

Kuo-Hua Chen

Ming-Han Wang

John Richard Hunt

Tsun-Lung Hsieh

Shao-An Chen

Chung-Hung Lai

Chia-Hsing Chou

Mi-Chun Hung

Ping Cing Shen

A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

Semiconductor package structure and method for manufacturing the same

A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

Package structure and testing method

An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

Electronic device package and method of manufacturing the same

An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.

An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.

Assembly structure and method for manufacturing the same

At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.

Wiring package and method of manufacturing the same

A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

Stacked semiconductor package assemblies including double sided redistribution layers

At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.

Semiconductor device package and a method of manufacturing the same

A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first contact pad and a second contact pad disposed on an upper surface of the semiconductor device. The semiconductor device package further includes a conductive bar disposed on the first contact pad, and a conductive pillar disposed on the second contact pad. A method of making a semiconductor device package includes (a) providing a substrate; (b) mounting a semiconductor device on the substrate, wherein the semiconductor device comprises a first contact pad and a second contact pad on an upper surface of the semiconductor device; (c) forming a dielectric layer on the substrate to cover the semiconductor device; (d) exposing the second contact pad by forming a hole in the dielectric layer; and (e) applying a conductive material over the dielectric layer and filling the hole.

Semiconductor device package and method of making the same

The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

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Kaohsiung, Taiwan

Chih-Yi Huang