Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Neuchips Corporation

Chih-wei Chang

Ming-Hsing Tsai

Wei-Jung Lin

Chun-Hsien Huang

Hung-Hsu Chen

Ya-Yi Cheng

Chun-chi Yu

Wei-Yip Loh

Yan-Ming Tsai

Min-Hsiu Hung

Yi-Hsiang Chao

Lin-Yu Huang

Sheng-Hsuan Lin

Hung-Yi Huang

Hong-Mao Lee

Chien Chang

Pin-Wen Chen

Kan-Ju Lin

Kai-Chieh Yang

Fu-chin Tsai

Yu-Chen Ko

Yu-Ting Wen

Peng-Hao Hsu

Shih-Chang Chen

Yu-Wen Cheng

Ger-Chih Chou

I-Li Chen

Yu-Shiuan Wang

Meng-kai Hsu

Chang-Ting Chung

Chih-Shiun Chou

Hui-Zhong Zhuang

Po-Hsiang Huang

Jerry Chang Jui Kao

Cheng-Tung Lin

Chih-Hao Wang

Li-Wei Chu

Yu-Kai Chen

Fong-Yuan Chang

Gerchih Chou

Sheng-Tsung Wang

Po-Yu Chen

Ching-Yi Chen

Chia-Han Lai

Ting-Yu Yeh

Han-Hsiang Huang

Wei-Ling Chang

Youn-Long Lin

Yu-Shih Wang

Hung-Chang Hsu

Mei-Hui Fu

Jyh Chwen Frank Lee

Yu-Ming Huang

Kuo-Wei Chi

Ying-Chi Su

Jian-Wen Chen

Ching-Yi Lin

Anurag Verma

Min-Han Tsai

Kevin Lee

Min-Hsuan Lu

Yuan-Chen Hsu

Harry Chien

Sang-Chi Huang

Pei-Wen Wu

Shu-Lan Chang

Yi-Ning Tai

Shang-chih Hsieh

Shih-Wei Yeh

Chih-Sheng Chou

Shi-han Zhang

You-cheng Lai

Pei Shan Chang

TaiMin Chang

YuShan Ruan

Pei-Wei Liao

Ting-Wei Weng

Shu-Ting Yang

Chun-Hsien Wen

Tai Min Chang

The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Conductive feature formation and structure using bottom-up filling deposition

A semiconductor device includes a first connector, a second connector, and a redistribution structure disposed between the first connector and the second connector. The redistribution structure includes a first connection tree electrically connecting the first connector to the second connector. The first connection tree includes a plurality of first conductive pads disposed in a plurality of respective levels, and a plurality of first via structures each disposed between adjacent ones of the plurality of first conductive pads. Any lateral end of each of the plurality of first conductive pads is spaced from the first connector within a first minimum pitch associated with the second connector.

Power delivery structures and methods of manufacturing thereof

A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.

Semiconductor device pre-cleaning

A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

Semiconductor device structure and method for forming the same

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Memory system, memory access interface device and operation method thereof

A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

Contact features of semiconductor device and method of forming same

A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.

Method for forming dual silicide in manufacturing process of semiconductor structure

A physical layer (PHY) circuit, a write leveling training circuit and a method for calibrating an access control signal are provided. The PHY circuit includes the write leveling training circuit, a clock generator and a transmitting (TX) logic. The write leveling training circuit generates at least one phase control signal. The clock generator outputs at least one control clock according to the phase control signal. The TX logic generates the access control signal according to the control clock, wherein a phase of the access control signal is associated with the phase control signal. The memory device outputs a data signal according to a phase error between a memory clock and the access control signal, and the write leveling training circuit determines a target value of the phase control signal according to the data signal, in order to minimize the phase error between the memory clock and the access control signal.

Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device

A method includes depositing an inter-layer dielectric (ILD) over a source/drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region; forming a metal-semiconductor alloy region on the source/drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

Transistor source/drain contacts and methods of forming the same

A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Fin field-effect transistor device and method of forming the same

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Contact with a silicide region

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.

Methods of forming semiconductor device structures

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Semiconductor structure and method of forming the same

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Memory system and memory access interface device thereof for supporting different speed modes

A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Systems and methods of estimating thermal properties of semiconductor devices

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HSINCHU, Taiwan

Chih-wei Chang