Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Au Optronics Corporation

Sitronix Technology Corporation

Coretronic Corporation

Mediatek Corporation

Mstar Semiconductor, Inc.

Globalwafers Co., Ltd.

Harvatek Corporation

Rays Optics Inc.

Chih-Wei Chang

Sheng-Hsuan Lin

Yu-Hung Lin

Wei-Yip Loh

Hung-Hsu Chen

Shau-Lin Shue

You-Hua Chou

Chii-Ming M Wu

Wei-Jung Lin

Chun-Chi Yu

Ming-Hsing Tsai

Mei-Yun Wang

Yan-Ming Tsai

Gerchih Chou

Chun-Hsien Huang

Hung-Yi Huang

Li-Wei Chu

Sung-Li Wang

Cheng-Tung Lin

Fu-Chin Tsai

Huang-Yi Huang

Ken-Yu Chang

Chun-I Tsai

Min-Hsiu Hung

Pin-Wen Chen

Shih-Chang Chen

Chia-Lin Hsu

Chun-Wen Nieh

Ching-Hwanq Su

Yu-Kai Chen

Jyh-Cherng Sheu

Hong-Mao Lee

Shen-Kuo Huang

Kuo-Wei Chi

Ying-Chi Su

Chi On Chui

Huicheng Chang

Ziwei Fang

Keng-Chu Lin

Su-Hao Liu

Shuen-Shin Liang

Chia-Hung Chu

Hsu-Kai Chang

Ching-Yi Chen

Yi-Hsiang Chao

Chung-Ting Wei

Yu-Wen Cheng

Yu-Shiuan Wang

Chien-Hao Chen

Chien Chang

Hung-Chang Hsu

Ya-Yi Cheng

I-Li Chen

Chiang-Ming Chuang

Ching-Fu Yeh

Chia-Han Lai

Mei-Hui Fu

Yu-Ming Huang

Kan-Ju Lin

Yee-Chia Yeo

Mong-Song Liang

Wei-Cheng Lin

Ming-Huan Tsai

Yu-Min Chang

Chao-Hsien Peng

Meng-Kai Hsu

Ju-Wang Hsu

Tsung-Han Wu

Chun-chi Yu

Ger-Chih Chou

Chin-Sheng Chao

Hui-Zhong Zhuang

Ting-Wei Chiang

Xiangdong Chen

Pang-Yen Tsai

Shyi-Ming Pan

Jerry Chang Jui Kao

Chih-Ming Hung

Shing-Chyang Pan

Chen-Yuan Kao

Chi-On Chui

Zhi-Ting Ye

Chu-Yun Fu

Yuan-Hung Chiu

Yung-Chen Chien

Yao-Chi Wang

Peng-Fu Hsu

Yi-Chun Lin

Ming-Lung Chen

Yu Shih Wang

Kun-Hung Hsieh

Shih-Wei Chou

Kuo-Chun Hsu

Chen-Cheng Lee

Keng-Meng Chang

Hsueh-Hung Fu

Tsung-Hsun Huang

Ting-Ying Wu

Super Liao

Chih-Chien Chang

A wearable display device includes an optical waveguide element and a projection device. The projection device includes an optical engine main body, at least one light emitting unit, an optical combiner, and a projection lens. The optical engine main body has at least one positioning structure. The light emitting unit is connected to the optical engine main body and configured to emit an illumination beam. The optical combiner is disposed in the optical engine main body and positioned at the positioning structure, the optical combiner is located on a transmission path of the illumination beam, and the optical combiner is configured to guide the illumination beam to form an image beam. The projection lens is connected to the optical engine main body, and the projection lens is located on a transmission path of the image beam and configured to project the image beam to the optical waveguide element.

Wearable display device and projection device

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes an epitaxial structure and a metal silicide layer. The epitaxial structure includes a semiconductor material. The metal silicide layer is disposed on the epitaxial structure. The metal silicide layer includes the semiconductor material, a first metal material and a second metal material. An atomic size of the first metal material is greater than an atomic size of the second metal material, and a concentration of the first metal material in the metal silicide layer varies along a thickness direction.

Semiconductor structure and manufacturing method thereof

An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Ammonium fluoride pre-clean protection

Semiconductor device pre-cleaning

A wearable display device, including an optical waveguide element and a projection device, is provided. The projection device includes an optical engine main body, a light emitting unit, an optical combiner, a projection lens, and a connection assembly. The light emitting unit is connected to the optical engine main body and configured to emit an illumination beam. The optical combiner is disposed in the optical engine main body, located on a transmission path of the illumination beam, and configured to guide the illumination beam to form an image beam. The projection lens is connected to the optical engine main body, located on a transmission path of the image beam, and configured to project the image beam. The connection assembly includes a flexible circuit board and a system connector. The light emitting unit is connected to the flexible circuit board and electrically connected to the system connector.

The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.

Field effect transistor contact with reduced contact resistance

Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Selective dual silicide formation

The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Capping layer for liner-free conductive structures

The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ┌P┐.

Data transmission apparatus and method having clock gating mechanism

A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.

Treatment for adhesion improvement

A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Phase control in contact formation

Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

DDR SDRAM signal calibration device and method

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Semiconductor device

In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Interconnect structures including a fin structure and a metal cap

Growing community of inventors

Hsin-Chu, Taiwan

Chih-Wei Chang