Faraday Technology Corporation

Tsinghua University

Chih-Wea Wang

Cheng-Wen Wu

Chi-Feng Wu

Chih-Kang Chiu

Jin-Fu Li

Chung-Chiang Teng

Chih-Tsun Huang

Kao-Liang Cheng

In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction

A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Built-in programmable self-diagnostic circuit for SRAM unit

Growing community of inventors

Taipei Hsien, Taiwan

Chih-Wea Wang