Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Teng Liao

Tzu-Chan Weng

Yi-Wei Chiu

Chih Hsuan Cheng

Yi-Jen Chen

Yu-Li Lin

Chih-Shan Chen

Jui Fu Hsieh

Chih-Hsuan Lin

Xi-Zong Chen

Hsi Chung Chen

Yu-Ling Ko

Chia-Chi Yu

Wan-Chun Kuan

Kun-Yu Lin

Yu-Chi Lin

Ying Ting Hsia

Chen-Wei Pan

Yi-Tsang Hsieh

Chih-Ching Cheng

Chia-Tsung Tso

Chia-Cheng Tai

En-Ping Lin

Yu-Hsi Tang

Yan-Ting Shen

Huai-Tei Yang

Li-Te Hsu

Lun-Kuang Tan

Cheng-Hung Tsai

Chia-Ching Tsai

Wei-Jen Lo

Po-Ju Chen

Jen-Chih Hsueh

I-Chen Chen

Chen-Fon Chang

Ying-Yu Lai

Hsiao Chien Lin

I-Chung Wang

Sheng-Kai Jou

Chun-Hung Liu

Cha-Hsin Chao

Chun-Yi Wu

Jiann-Horng Lin

Chih-Lun Lu

Hsiu-Ling Chen

Jih-Sheng Yang

Lin-Ting Lin

Jui Fu Hseih

Kun-Cheng Chen

Yu-Lun Ke

Shi-Yu Ke

Yu Hsi Tang

Ji-Ling Wu

Jun Shimada

Shu Wen Wang

Dave Lo

Sheng-Jen Cheng

Huang-Shao Ko

Zheng-En Bao

Chen Yung-Chan

Chi-Hsing Lin

Jui-Fu Hsieh

Po-Lung Hung

Liang Yu Chen

Yun-Jui He

Li-Feng Chu

Bo-Ting Liao

Yung-Chang Jen

Tsung-Yi Tseng

Shao Yong Chen

Some implementations described herein provide techniques and apparatuses for improving a uniformity of a flow of a gas across a semiconductor substrate in an etch tool. The etch tool includes an exhaust port located at a bottom center of a chamber of the etch tool. The etch tool further includes a flow-control subsystem that includes an impeller and a thermal component. As a result of the flow-control subsystem varying a rotational velocity of the impeller, and/or an amount of heat transferred from the thermal component, the uniformity of the flow of the gas across the semiconductor substrate may be improved. In this way, a uniformity of an etching rate may be increased and contamination defects due to a clustering of particulates may be decreased, resulting in an increase in a yield of semiconductor product fabricated using the etch tool.

Semiconductor processing tool and methods of operation

A semiconductor device having source and drain regions in a semiconductor substrate, a transistor including a gate electrode over the semiconductor substrate, an isolation structure in the semiconductor substrate adjacent to the transistor, a first inter-dielectric layer (ILD) material over the isolation structure, and a capacitor film stack over the first ILD material that includes an isolation plate over and covering a capacitor plate, and a contact to the capacitor plate.

Semiconductor device with short-resistant capacitor plate

A recovery layer (e.g., a layer of organic and/or tin-based material) is formed within recesses, in which adjacent MEOL or BEOL structures are formed, after plasma ashing and before a trimming process. The recovery layer preserves hardmask material and dielectric material such that upper surfaces of the adjacent MEOL or BEOL structures remain physically separated. As a result, the adjacent MEOL or BEOL remain electrically isolated and functional.

Semiconductor structure formation

A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.

Extended side contacts for transistors and methods forming same

A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

Source and drain structure with reduced contact resistance and enhanced mobility

An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

Method for forming recesses in a substrate by etching dummy fins

Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

Transistor gate structure and process

A method of forming a semiconductor device includes providing a device having a gate stack with a metal gate layer and a spacer layer disposed on a sidewall of the gate stack. In some embodiments, the method further includes performing an etch-back process to the metal gate layer to form an opening over the gate stack. In various examples, the method further includes performing a plasma treatment process to modify a profile of the opening. In some cases, the method further includes forming a HM layer over the metal gate layer and within the opening having the modified profile.

Metal gate process and related structure

A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

Fin height and STI depth for performance improvement in semiconductor devices having high-mobility p-channel transistors

A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.

Dry etcher uniformity control by tuning edge zone plasma sheath

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Method of manufacturing a semiconductor device and a semiconductor device

A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

Semiconductor device and method

A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

Semiconductor structure and method for manufacturing thereof

Methods for revitalizing components of a plasma processing apparatus that includes a sensor for detecting a thickness or roughness of a peeling weakness layer on a protective surface coating of a plasma processing tool and/or for detecting airborne contaminants generated by such peeling weakness layer. The method includes detecting detrimental amounts of peeling weakness layer buildup or airborne concentration of atoms or molecules from the peeling weakness layer, and initiating a revitalization process that bead beats the peeling weakness layer to remove it from the component while maintaining the integrity of the protective surface coating.

Method and apparatus for revitalizing plasma processing tools

A dummy gate structure may be formed for a semiconductor device. The dummy gate structure may be formed from an amorphous polysilicon layer. The amorphous polysilicon layer may be deposited in a blanket deposition operation. An annealing operation is performed for the semiconductor device to remove voids, seams, and/or other defects from the amorphous polysilicon layer. The annealing operation may cause the amorphous polysilicon layer to crystallize, thereby resulting in the amorphous polysilicon layer transitioning into a crystallized polysilicon layer. A dual radio frequency (RF) source etch technique may be performed to increase the directionality of ions and radicals in a plasma that is used to etch the crystallized polysilicon layer to form the dummy gate structure. The increased directionality of the ions increases the effectiveness of the ions in etching through the different crystal grain boundaries which increases the etch rate uniformity across the crystallized polysilicon layer.

Forming a dummy gate structure

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Hsinchu, Taiwan

Chih-Teng Liao