Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Pin Chiu

Dian-Hau Chen

Chen-Chiu Huang

Liang-Wei Wang

Chih-Fan Huang

Chien-Hua Huang

Yuan-Yang Hsiao

Hung-Chao Kao

Mao-Nan Wang

Yu-Jen Wang

Ying-Yao Lai

Chang-Lin Yang

Chih-Chuan Su

Chen-Te Chu

Tzu-Ting Liu

Zhen De Ma

Lee-Wen Hsu

A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than −0.3 GPa.

Semiconductor packaging structure and method for manufacturing the same

A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.

Wafer test pad

A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.

Semiconductor memory structure and method for forming the semiconductor memory structure

Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

Method for manufacturing semiconductor structure with memory device

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Hsinchu, Taiwan

Chih-Pin Chiu