Other

Taiwan Semiconductor Manufacturing Comp. Ltd.

Sitron Precision Co., Ltd.

Kingtron Electronics Co., Ltd.

Fu Sheng Industrial Co., Ltd

Walsin Advanced Electronics Ltd.

Domintech Co., Ltd.

Chih-Kung Huang

Shin-Puu Jeng

Po-Yao Lin

Shu-Shen Yeh

Shyue-Ter Leu

Wei-Jen Lai

Shu-Hua Tseng

Tsung-Ming Yeh

Hui-Chang Yu

Wen-Chun Liu

Jeff Biar

Kazuhiro Okada

Ming-Ching Wu

Jung-Jie Liou

Chin-Fu Chung

Ying-Chih Chen

Jin-Chyuan Biar

Meng-Tsung Kuo

Wei-Teng Chang

Wei Teng Chang

Jue E-Yin Huang

Dyi-Chung Hu

Chien-Nan Wu

A disclosed semiconductor device includes a package substrate, a first semiconductor die coupled to the package substrate, a package lid attached to the package substrate and covering the semiconductor die, and a thermal interface material located between a top surface of the semiconductor die and an internal surface of the package lid. The semiconductor device may further include a dam formed on the internal surface of the package lid. The dam may constrain the thermal interface material on one or more sides of the first semiconductor die such that the thermal interface material is located within a predetermined volume between the top surface of the first semiconductor die and the internal surface of the package lid during a reflow operation. The package lid may include a metallic material and the dam may include an epoxy material formed as a single continuous structure or may be formed as several disconnected structures.

Dam structure on lid to constrain a thermal interface material in a semiconductor device package structure and methods for forming the same

A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.

Structure and formation method of chip package with protective lid

A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

Semiconductor device and method of manufacture

A MEMS sensor capable of sensing acceleration and pressure includes a frame, a proof mass and flexible bridges connected between the frame and the proof mass in such a way that the proof mass is moveably suspended inside the frame. The proof mass is provided with a pressure sensing diaphragm and a sealed chamber corresponding to the diaphragm such that the proof mass is not only served as a moveable sensing element for acceleration measurement but also a pressure sensing element.

MEMS sensor capable of sensing acceleration and pressure

A light-emitting element package including a heat conductive layer having a first surface and a second surface, a dielectric layer disposed on the first surface of the heat conductive layer and having an opening exposing the heat conductive layer, two electrodes disposed on the dielectric layer at a side far away from the heat conductive layer, a light-emitting element, and a transparent sealing layer. The light-emitting element is disposed in the opening, carried on the first surface of the heat conductive layer, and electrically coupled to the two electrodes. The transparent sealing layer encapsulates the light-emitting element, the heat conductive layer, and the two electrodes, and exposes part of the two electrodes and the second surface of the heat conductive layer.

Light-emitting element package and light source apparatus using the same

A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a through opening with a diameter larger that the diameter of the through opening of the base metal member; the active member being coupled with the carrier member in such a way that the intermediate layer is adhered to an upper surface of the carrier member, and these through openings are aligned to define a shoulder around the through opening of the base metal plate.

Base substrate for chip scale packaging

A method of fabricating a film carrier is provided. The method comprises the steps of providing a film; forming a metallic layer on the film, patterning the metallic layer by etching to form a plurality of metallic leads; and, patterning the film by etching to form a plurality of openings so that processing time and manufacturing cost are reduced.

Method of fabricating film carrier

A tape structure and method of fabricating the tape structure. The method includes plating a metal such as silver, bismuth, gold, magnesium, nickel, or palladium over leads so that recess cavities and whiskers on the leads are greatly reduced.

Tape structure and manufacturing method

A bonding pad structure. A substrate having a first surface and a second surface is provided. A metal bonding pad and a bonding region are respectively located on the first surface and the second surface. Intermediate plated layers located are on the metal bonding pad and the bonding region. Under ball metallurgy layers are located on each of the intermediate plated layers such that each of the under ball metallurgy layers comprises a first plated layer and a second plated layer.

Bonding pad structure and method for fabricating the same

A chip scale package, which can be fabricated on a print circuit board, comprises a chip having multiple electrodes, a plurality of conductive blocks, and an insulating material. The electrodes of the chip are electrically connected to the conductive blocks respectively through one of the surfaces thereof by a conductive bond, and are electrically connected to the circuit on the print circuit board through the side surfaces thereof. The insulated material is filled on the chip surface between the conductive blocks, and in the gap between the conductive blocks and the chip.

Chip scale package of semiconductor

A dual-chip packaging structure comprises a die pad with a chip attached to each of its two surfaces. Outside and around the die pad is a plurality of first metal studs. A plurality of second metal studs is arranged outside and around the first metal studs. Connections between the first metal studs and the second metal studs are made by means of a plurality of conductive traces. The two chips on the respective surfaces of the die pad are connected to corresponding ends of the first metal studs through bonding wires. An insulating material is employed to enclose the two chips, the die pad, the first metal studs, the conductive traces, and ends of the second metal studs, with other ends of the second metal studs exposed. A plurality of solder balls is attached to the respective exposed ends of the second metal studs.

Dual-chip packaging

The addition of a heat slug to a lead frame establishes a heat conduction path from a silicon chip on the lead frame to the heat slug. Hence, when a semiconductor package that encloses the lead frame and the silicon chip is formed, heat produced by the silicon chip can still be channeled away through the radiating surface of the heat slug. Furthermore, the heat slug can be bent over to cover burrs outside the package.

Lead frame with heat slug

A dual leadframe package. A chip including a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first lead including a first innerlead and a first outerlead and a second lead including a second innerlead and a second outerlead are provided. The first innerlead is coupled to the first source/drain region, and the second innerlead is coupled to the gate. A conductive plate including a top surface and a bottom surface is provided, and the top surface is coupled to the second source/drain region. A packaging material seals the chip, the first innerlead, the outerlead and a portion of the conductive plate. The bottom surface, the first outerlead and the second outerlead are exposed.

Growing community of inventors

Hsinchu, Taiwan

Chih-Kung Huang