Vanguard International Semiconductor Corporation

Mediatek Corporation

Chih-Hung Lin

Chia-Hao Lee

Chun-Chia Chen

Shin-Cheng Lin

Chih-Cherng Liao

Ming-Luen Liou

Yih-Ming Tsuie

Po-Heng Lin

Syed-Sarwar Imam

Ming-Han Weng

Chien-Huei Lin

Wei-Yung Wang

Wei-Tsen Lin

Jyun Yang Shih

Kun-Han Lin

A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.

Semiconductor device and fabrication method thereof

A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.

Semiconductor structure

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first well region, a second well region, an isolation structure, and a gate structure. The first well region is disposed in the substrate. The second well region is disposed in the substrate. The second well region is adjoining the first well region. The isolation structure is disposed in the first well region. The gate structure is disposed on the substrate. The gate structure includes a first gate portion and a second gate portion. The first gate portion overlaps the first well region and the second well region. There is an opening between the first gate portion and the second gate portion exposing a portion of the isolation structure.

Semiconductor structure and method of forming the same

Tool handle

A semiconductor device is provided. The semiconductor device includes a substrate, an oxide layer disposed over the substrate, and a first epitaxial layer disposed over the oxide layer. The first epitaxial layer has the first conductivity type. The semiconductor device also includes a second epitaxial layer disposed over the first epitaxial layer and a third epitaxial layer disposed over the second epitaxial layer. The second epitaxial layer has a second conductivity type that is opposite to the first conductivity type. The third epitaxial layer has the first conductivity type.

Semiconductor substrate structure and semiconductor device and methods for forming the same

An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.

Method for determining sampling phase of sampling clock signal and associated electronic device

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first oxide layer disposed over the substrate, a second oxide layer, and a semiconductor layer disposed over the second oxide layer. The second oxide layer is disposed at one side of the first oxide layer and is in contact with the first oxide layer. The second oxide layer partially overlaps the first oxide layer, and the first oxide layer and the second oxide layer include the same oxide.

Semiconductor structure and method for forming the same

A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.

Growing community of inventors

Taichung, Taiwan

Chih-Hung Lin