United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

United Semiconductor Corp.

Chih-Hung Cheng

Wen-Chih Chiou

Shih-Hung Chen

Yung-Chi Lin

Hsuan-Hsu Chen

Yi-Tyng Wu

Shih-Hui Wang

Chien-hua Tsai

Huai-Hsuan Tsai

A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.

Semiconductor manufacturing process and package carrier

A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.

Process for fabricating micro-display

A method for fabricating salicide devices over a substrate is described. The substrate has a gate structure pair in which a first gate structure comprises a first gate and a first stuffed film located on the first gate, and a second gate structure comprises a second gate and a second stuffed film located on the first gate. A first spacer is formed on the sidewall of the first gate structure. A second spacer is formed at the sidewall of the second gate structure. The first and the second stuffed films are removed. The second spacer is etched back so as to form a third spacer lower than the second gate. Salicide layers are formed upon the first and the second gates.

Method for forming salicide layers

A method of chemical-mechanical polishing. A die region and a scribe line region are defined on a wafer. A dummy pattern is formed in the scribe line region. A dielectric layer is formed to cover the dummy pattern and the wafer. The dielectric layer is planarized by chemical-mechanical polishing.

Method of chemical-mechanical polishing

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Hsinchu, Taiwan

Chih-Hung Cheng