Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Hui Huang

Yeur-Luen Tu

Sheng-Chan Li

Cheng-Hsien Chou

Chia-Shiung Tsai

Cheng-Yuan Tsai

Sheng-Chau Chen

Dun-Nian Yaung

Cheng-Ta Wu

Shih Pei Chou

Kuo-Ming Wu

Jung-Chih Tsao

Yao-Hsiang Liang

Chi-Ming Lu

Ching-Chun Wang

Ping-Yin Liu

Xiaomeng Chen

Yen-Chang Chu

Chun-Han Tsao

Jen-Cheng Liu

Feng-Chi Hung

Shyh-Fann Ting

Chih-Yu Lai

Jeng-Shyan Lin

Lan-Lin Chao

Xin-Hua Huang

Shu-Ting Tsai

Yung-Lung Lin

Kuo-Hwa Tzeng

Chih-Chang Huang

Hau-Yi Hsiao

Chia-Chieh Lin

Ching-Ho Hsu

Jhy-Jyi Sze

Szu-Ying Chen

Chen-Jong Wang

Ru-Liang Lee

Hsiao-Hui Tseng

Yen-Ting Chiang

Cheng-Yi Wu

Yi-Ming Lin

Kuan-Liang Liu

Jian-Shin Tsai

Chao-Ching Chang

Luan Conn Tran

Min-Hui Lin

Yan-Chih Lu

Xiao-Meng Chen

Chun-Chieh Chuang

Chin-Szu Lee

Shih-Pei Chou

Tung-Ting Wu

Yu-Cheng Tsai

Ju-Shi Chen

Wen-Jen Tsai

Chia-Hsing Chou

Chia-Chiung Tsai

The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.

Method for wafer bonding including edge trimming

The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Multi-wafer capping layer for metal arcing protection

A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Method of forming semiconductor device

A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Interconnect structure for stacked device

A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCN, and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.

Method of forming deep trench isolation in radiation sensing substrate and image sensor device

An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.

Wafer bonding method and apparatus with curved surfaces

A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising NO, Nand Othrough a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.

Manufacturing methods of semiconductor image sensor devices

In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

Bonding support structure (and related process) for wafer stacking

The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.

Method for manufacturing semiconductor device and manufacturing method of the same

A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.

Gas shower head with plural hole patterns and with corresponding different plural hole densities and film formation method

Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.

Reflector for backside illuminated (BSI) image sensor

Growing community of inventors

Yongkang, Taiwan

Chih-Hui Huang