Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Hsuan Tai

Hao-Yi Tsai

Yu-Chih Huang

Ting-Ting Kuo

Ying-Cheng Tseng

Chung-Shi Liu

Ban-Li Wu

Chen-Hua Douglas Yu

Chih-Hua Chen

Chia-Hung Liu

Chi-Hui Lai

Chiahung Liu

Chih-Wei Lin

Yu-Chia Lai

Tsung-Hsien Chiang

Tin-Hao Kuo

Kuo-Lung Pan

Po-Chun Lin

Yu-Feng Chen

Yu-Jen Cheng

Ming-Da Cheng

Ching-Hua Hsieh

Hsiu-Jen Lin

Chun-Cheng Lin

Mao-Yen Chang

Hung-Yi Kuo

Cheng-Chieh Hsieh

Chung-Ming Weng

Hsiang-tai Lu

Ming-Chung Wu

Chuei-Tang Wang

Chih-Hao Chang

Pei-Hsuan Lee

Chien-Ling Hwang

Chih-Horng Chang

Hsiao-Chung Liang

Kuo-Wen Chen

Kuo Wen Chen

Tsung-Yuan Yu

Min-Hsiang Hsu

Hsiang-Tai Lu

Hua-Kuei Lin

Yu-wei Chiu

A method of manufacturing a semiconductor structure, comprising: disposing a dielectric layer over a semiconductive wafer defined with a plurality of active regions and a scribe line region surrounding each of the plurality of active regions; forming a plurality of interconnect structures within the dielectric layer, wherein the formation of the plurality of interconnect structures includes forming a plurality of first testing pads within the scribe line region and at least partially exposed through the dielectric layer; and sawing the semiconductive wafer along the scribe line region to form a first interposer and a second interposer, wherein each of the plurality of first testing pads is at least partially removed by the sawing of the semiconductive wafer.

Semiconductor structure with testing pads and method of manufacturing thereof

A package structure includes an insulating encapsulation, a semiconductor die, and a redistribution circuit structure. The semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure includes conductive patterns, wherein the conductive patterns each comprise a first portion, at least one second portion, and at least one connecting portion. A first edge of the at least one connecting portion is connected to the first portion, and a second edge of the at least one connecting portion is connected to the at least one second portion, wherein the first edge is opposite to the second edge, and a length of the first edge is greater than a length of the second edge.

Package structure with conductive patterns in a redistribution layer

A semiconductor structure includes a substrate, a capacitor disposed in the substrate, an interconnect structure disposed over the substrate, and a first doped region disposed in the substrate. The interconnect structure includes a first via structure coupled to the substrate, and a second via structure coupled to the capacitor. The first doped region is disposed under the first via structure. The first doped region includes p-type or n-type dopants.

Semiconductor package structure and method for forming the same

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

Package structure and method of forming the same

A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Method of fabricating semiconductor structure including a barrier structure in between a plurality of surface mount components and a wafer

An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.

Package and method of forming same

In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Sensor packages

Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

Delamination sensor

A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

Package structure with through via extending through redistribution layer and method of manufacturing the same

A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Package structure, package-on-package structure and method of fabricating the same

Package structure with through-via in molding compound and dielectric layer

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Taipei, Taiwan

Chih-Hsuan Tai