Mediatek Corporation

Benq Corporation

Chih-Hsin Lin

Tsung-Huang Chen

Bing-Shiun Wang

Jen-Pin Su

Hsin-Chung Yang

A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data.

DDR PSRAM and data writing and reading methods thereof

A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.

A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

Controller and access method for DDR PSRAM and operating method thereof

A protecting circuit for a horizontal transistor used for protecting the horizontal transistor of a horizontal deflecting circuit in a cathode ray tube. The protecting circuit comprises a switching circuit and a power sensor. The switching circuit is coupled to at least one sub capacitor of a S-character correcting loop. When the switching circuit is on, the switching circuit further connects the sub capacitors and the main capacitor of the S-character correcting loop in parallel. The power sensor is for detecting whether the D.C. voltage source is on. When the power sensor detects that the D.C. voltage source is off, the power sensor will turn on the switching circuit. The invention reduces a surge of the cross voltage V of the horizontal transistor when the system is off, therefore the invention achieves the goals of protecting the horizontal transistor and raising yield of the products.

Growing community of inventors

Taoyuan, Taiwan

Chih-Hsin Lin