Via Technologies, Inc.

Chih Hsien Weng

Cheng-Yuan Wu

Chen-Hua Hsi

Stone Wei

A method for coordinating packet transmission order for a plurality of registers of different priority levels is disclosed. Packets are transmitted from the registers according to the priority levels in a normal condition. A count value is generated in response to the transmitted packets. A particular priority level of one of the registers, from which a packet is being transmitted out, is recorded when the count value is larger than a predetermined threshold. Then the normal condition switches into a cleaning condition, and one packet is transmitted from each of the registers which are not empty and have priority levels lower than the particular priority level according to priority. Finally, reset the count value, and return to the normal condition. A device for coordinating packet transmission order for a plurality of registers of different priority levels is also disclosed.

Method and device for coordinating packet transmission order

A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.

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Taipei, Taiwan

Chih Hsien Weng