Taiwan Semiconductor Manufacturing Comp. Ltd.

Sintai Optical (shenzhen) Co., Ltd.

Asia Optical International Ltd.

Chih-Hsien Lin

Hsiang-Tai Lu

Dai-Jang Chen

Shin-Puu Jeng

Chen-Hua Lin

Ching-Fang Chen

Shuo-Mao Chen

Shyh-Chyi Wong

Feng-Cheng Hsu

Mill-Jer Wang

Chao-Hsiang Yang

Cheng-Yi Hong

Chi-Feng Huang

Yung-Cheng Lu

Tzyh-Cheang Lee

Tzy-Kuang Lee

Yen-Chao Chen

Kong-Beng Thei

Yen-Yu Chen

Wen-Chun Wang

Po-Yao Chuang

Bruce C S Chou

Ching-Hung Kao

Hsien-Wen Liu

Shih-Ting Hung

Jung-Kuo Tu

Hui-Lin Chang

Mingo Liu

Tsung-Wei Lin

Meng-lin Chung

Tung-Hung Hsieh

Wen-Chien Chang

Szu-Han Wu

Jen-Chih Chung

Yung-Sheng Chiang

Chen-Hua Douglas Yu

Jing-Cheng Lin

Ming-Da Cheng

Wen-Chih Chiou

Syun-Ming Jang Jang

Tien-I Bao

Po-Hao Tsai

Ching-Wen Hsiao

Chung-Chi Ko

Wen-Chun Huang

Jui-Feng Kuan

Hsi-Kuei Cheng

Kuo-Chio Liu

Chih-Ping Chao

Ming-Shih Yeh

Chien-Chen Li

Lih-Ping Li

Chun-Hon Chen

Ruey-Yun Shiue

Sung-Hsiung Wang

Hao Chun Liu

Heng-Ming Hsu

Tzi-Yi Shieh

Wenchi Ting

Wong-Cheng Shih

Wei-Sho Hung

Hsiang-tai Lu

Lin-Ping Li

Shyh-Chyi Wang

Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

Redistribution layer features

A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Semiconductor structure and manufacturing method thereof

A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

Circuit test structure and method of using

A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

Passivation layer and planarization layer and method of forming the same

A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

A circuit test structure includes an interposer for electrically connecting to a chip, wherein the interposer includes a conductive line, and the conductive line extends along at least two side of the interposer. The circuit test structure further includes a plurality of electrical connections to the conductive line. The circuit test structure further includes a testing site electrically connected to the conductive line, wherein the testing site is on an opposite surface of the interposer from the plurality of electrical connections.

A circuit test structure including an interposer for electrically connection to a chip, wherein the interposer includes a conductive line, and the conductive line traces a perimeter of the interposer. The circuit test structure further includes at least three electrical connections to the conductive line. The circuit test structure further includes a testing site. The circuit test structure further includes a through substrate via (TSV) connecting the testing site to the conductive line.

Circuit test structure

An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

Integrated fan-out packages

A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line.

A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Package structure and methods of forming same

A trajectory prediction system for predicting a point of impact of an object shot from a ballistic device is provided. The trajectory prediction system includes an objective lens, an eyepiece lens optically coupled with the objective lens, an image sensor, a processor, and a display electrically connected to the processor and the image sensor. The image sensor, the processor, and the display are disposed between the objective lens and the eyepiece lens. When an external light reaches the image sensor through the objective lens, the image sensor transmits a first signal to the display, and the display shows an image according to the first signal. The processor calculates the trajectory of the object and transmits a second signal to the display, and the display simultaneously shows the image and at least one predictive point of impact according to the first and second signals.

Trajectory prediction system

Growing community of inventors

Tai-Chung, Taiwan

Chih-Hsien Lin