Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Hsiang Fan

Hsien-Ming Lee

Chi On Chui

Da-Yuan Lee

Yu-Sheng Wang

Wei-Chin Lee

Ya-Wen Chiu

Kun-Wa Kuok

Kai-Cyuan Yang

Tsung-Han Shen

Jia-Ming Lin

Chien-Hao Chen

Hsiao-Kuan Wei

Yi-Ting Wang

Jui-Fen Chien

Pohan Kung

Kevin Chang

Yu-Ming Li

A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Metal gate structure and method of forming the same

A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Void elimination for gap-filling in high-aspect ratio trenches

A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

CMOS finFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

Methods of fabricating semiconductor devices with metal-gate work-function tuning layers

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Hsinchu, Taiwan

Chih-Hsiang Fan