Integrated Device Technology, Inc.

Chih-Hsiang Chen

Guo-Qiang Lo

Shih-Ked Lee

Guo-Qiang Patrick Lo

Yiming Gu

S K Lee

Sidewall spacers are disclosed that extend on opposing sidewalls of gate stacks. The sidewall spacers have improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stackhaving a sidewall is formed over the gate dielectric layer. The gate stackcomprises a conductive layerand a hard maskoverlying the conductive layer. A lineris selectively deposited over the gate stacksuch that the lineris deposited on the hard maskat a rate lower than the rate of deposition on the conductive layer. Thus, the lineris substantially thinner on the hard maskthan on the conductive layer. A nitride spacer is formed overthe liner. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks.

Gate structures having sidewall spacers formed using selective deposition

The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate and an etch is performed so as to form trenches within the semiconductor substrate. A shallow trench isolation structure and a method for forming a shallow trench isolation structure are disclosed. Oxidation enhancing species are then implanted into the bottom surface of the trenches and an oxidation process is performed. The oxidation enhancing species will form a deep oxidation region below the bottom surface of each trench and will form thinner oxidation regions within side surfaces of trenches. A layer of dielectric material is then deposited to fill the trenches. A chemical mechanical polishing process is performed to remove those portions of the dielectric film that overlie the hard mask. The hard mask is then removed, producing a void-free shallow trench isolation structure.

Method for forming shallow trench isolation structure with deep oxide region

A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is performed so as to reduce the width of the hard mask on each of the gate film stacks, exposing portions of the top surface of the silicide layer. A second selective etch is then performed to reduce the width of the silicide layer. Spacers are then formed on opposite sides of each of the gate film stacks, and a dielectric film is formed that extends over the gate film stacks. By reducing the width of the hard mask layer and the silicide layer, gate film stacks are obtained that have reduced width near the top of each gate film stack, preventing voids from forming in the dielectric film.

Method for forming CMOS structure with void-free dielectric film

The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is performed so as to form trenches within the semiconductor substrate. An anti-reflective film is deposited such that it extends within the trench. A dielectric film is deposited over the anti-reflective film such that it fills the trench. A heating process step is then performed to anneal the substrate, rounding the corners of the trench. A chemical mechanical polishing process is performed to remove those portions of the anti-reflective film and the dielectric film that overlie the hard mask. The hard mask is then removed, producing a shallow trench isolation structure that prevents lifting and notching in subsequent fabrication steps.

Method for forming shallow trench isolation structure with anti-reflective liner

Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate structures over a semiconductor substrate. A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack having a sidewall is formed over the gate dielectric layer. The gate stack comprises a conductive layer and a capping nitride layer overlying the conductive layer A liner is selectively deposited over the gate stack such that the liner is deposited on the capping nitride layer at a rate lower than the rate of deposition on the conductive layer Thus, the liner is substantially thinner on the capping nitride layer than on the conductive layer A nitride spacer is formed over the liner A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks and substantially free of voids.

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Portland, OR, United States of America

Chih-Hsiang Chen