Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Fen Chen

Chui-Ya Peng

Yuh-Ta Fan

Yen Chuang

Bang-Yu Huang

Ching Yu

Pin-Hen Lin

Yeh-Hsun Fang

Tsung-Ying Liu

In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d) above the at least one first trench. A first depth parameter (t) of the second depth (d) relative to the first depth (d) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Method for calibrating temperature in chemical vapor deposition

A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Semiconductor device

In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d) above the at least one first trench. A depth parameter (t) the second depth (d) relative to the first depth (d) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.

A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.

A semiconductor device includes a substrate, a gate stack, at least one epitaxy structure, a dielectric material, and a contact. The gate stack is present on the substrate. The gate spacer is present on a sidewall of the gate stack. The epitaxy structure is partially present in the substrate. The dielectric material is present on the substrate and between the epitaxy structure and the gate spacer. The contact is present on the epitaxy structure, the dielectric material, and the gate spacer.

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Taoyuan, Taiwan

Chih-Fen Chen