Nan Ya Technology Corporation

Chih-Ching Lin

Shing-Yih Shih

Yi-Nan Chen

Tse-Yao Huang

Hsien-Wen Liu

Jeng-Ping Lin

Hui-Min Mao

Chiang-Lin Shih

Chang Rong Wu

Yu-Chi Sun

The present application provides a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a passivation disposed over the second substrate; a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Semiconductor structure having vias with different dimensions

The present application provides a method of manufacturing a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The method includes: providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; forming a passivation over the second substrate; forming a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and forming a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Method of manufacturing semiconductor structure having vias with different dimensions

A semiconductor structure includes a semiconductor device, an interconnect structure, a dielectric layer, and a redistribution layer (RDL). The interconnect structure is disposed over the semiconductor device. The dielectric layer is disposed over the interconnect structure. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via includes a bottom portion, a top portion and a tapered portion between the bottom and top portions, in which the tapered portion has a width variation greater than that of the bottom and top portions.

Semiconductor structure

A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A patterned photoresist layer is formed over the dielectric layer, wherein the patterned photoresist layer has an opening exposing the dielectric layer. The dielectric layer is etched to form a via hole in the dielectric layer using the patterned photoresist layer as an etch mask. The opening of the patterned photoresist layer is laterally expanded. After the opening of the patterned photoresist layer is laterally expanded, the dielectric layer is etched to expand the via hole using the patterned photoresist layer as an etch mask. A conductive via is formed in the expanded via hole.

Semiconductor structure and fabrication thereof

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer.

Semiconductor structure and method of manufacturing the same

A method of forming fine island patterns of semiconductor devices includes: forming a plurality of first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; patterning a plurality of islands in the upper buffer mask layer; separating each of the islands into a plurality of sub-islands; etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.

Method of forming fine island patterns of semiconductor devices

A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Method for forming openings in semiconductor device

A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

Method for forming fin-shaped semiconductor structure

A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Fabrication method for a damascene bit line contact plug

A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Interconnect structure and method for fabricating the same

A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.

Growing community of inventors

Taoyuan, Taiwan

Chih-Ching Lin